2D Scaler
1865 - Can I instantiate three "Single-color Plane" 2D Scaler IP cores, and output the three color planes in parallel?
Yes. Lattice's 2D Scaler IP core can be configured in either "Single-color Plane" mode or "Multi-color Plane" mode. In "Single-color Plane" mode, the scaler core can be instantiated three times to process the RGB or YCbCr color planes in parallel; in ...
5424 - CMOS-TO-DPHY IP: Why does the connection type is still "pad-pin"declared in Clarity even if the signal does not go to I/O pins but rather go to internal logic?
Solution Clarity Designer builder for modules and IP such as cmos-to-dphy is intended to be stand alone and thus it automatically generates a pad-pin type of connection. It is already a known issue when this IP module is used or connected as part of ...
2230 - The Power Manager Datasheet specifies Vol value of open drain outputs only at a particular current. Can I estimate Vol at different currents?
The Vol specification mentioned in the datasheet is the worst case value at a particular current. This worst case value has added margins so that the expected device performance is guaranteed. Thus, actual Vol on the device will be lower than this ...
3039 - [Color Space Converter (CSC) IP Core]: What is the meaning of tags_in and tags_out signals?
The input signal - tags_in - is some combined timings signals, such as hsync, vsync and so on. The output signal - tags_out - will only delay some clocks without any process compared with tags_in (same delay as data signals). The user can combine any ...
3038 - [LatticeECP3][2D Scaler IP]: Does the input data need to include the EAV/SAV Blanking for the 2D Scaler IP?
There is no need to input all the EAV (End of Active Video)/SAV (Start of Active Video) Blanking to the 2D Scalar IP core. The input data should be valid only when the "ready" signal out of the IP is asserted, otherwise the input data would be ...
3037 - [2D Scaler IP Core]: What input format does Lattice 2D Scaler IP (Intellectual Property) support- progressive or interlace?
The input of 2D Scaler IP is progressive. If the video source is in interlace format, the user has to use the "Deinterlacer" IP to convert the input data to progressive format before scaling.
3034 - [LatticeECP3]: Can the receiver logic of the Serial Digital Interface (SDI) Intellectual Property(IP) extract the right values if there is invalid line number and Video Payload Identifier (VPID)?
The line number and Video Payload Identifier (VPID) bytes are directly extracted from the input video stream. If they are invalid, the extracted line number and VPID will also be invalid. They are not corrected in the IP based on the extracted video ...
6138 - [ECP5]Can Tri-Rate Serial Digital Interface (SDI) PHY IP also support ECP5 devices?
Solution: The Tri-Rate Serial Digital Interface (SDI) PHY IP only supports ECP3 devices.
3752 - 7:1 LVDS Video Interface: Does Lattice have 7:1 LVDS Video Demo Kit which can be used for developing video-based applications, for example camera link interface?
The following Lattice demo kits are available for utilizing the 7:1 LVDS Reference Design: - ECP3 Video Protocol Board http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/LatticeECP3VideoProtocolBoard.aspx Refer to RD1030, 7:1 LVDS Video ...