The IP (Intellectual Property) reset signals of the Lattice IP cores are not connected to the GSR components by default. Hence, the users can connect their end design reset signals to the GSR component.
Description: The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) core asserts all MSI one after the other. The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) can handle up to 8 ...
Yes. Lattice's 2D Scaler IP core can be configured in either "Single-color Plane" mode or "Multi-color Plane" mode. In "Single-color Plane" mode, the scaler core can be instantiated three times to process the RGB or YCbCr color planes in parallel; in ...
Lattice CPRI IP core (Common Public Radio Interface) itself provides the auto-negotiation function. There is a state machine that will automatically go through a searching state from one line rate to the next line rate, eventually it will find the ...
There is no need to input all the EAV (End of Active Video)/SAV (Start of Active Video) Blanking to the 2D Scalar IP core. The input data should be valid only when the "ready" signal out of the IP is asserted, otherwise the input data would be ...