Demo & Reference Design Source Code
3630 - MachXO2: Will the command sequence implemented in the DCS ROM of the DSI TX reference design work for all displays?
The command sequence implemented in the DCS ROM of the Reference Design were taken from the source code of Android based working setup. The command sequence only works for the Wintek display described in the user guide. It is the responsibility of ...
3571 - LatticeECP3: How to use Dphase(3:0)
Dphase_sel, Dphase_lock, Rxpll_lock,
Dphase_out,
Rclk_out ports available in 7:1 LVDS reference design on a customized board?
The following ports in Lattice LVDS 7:1 loopback demo are used for testing purpose to show the status of these signals to the user: - status_out_sel, - Status_RCLK_out, - seven_seg, - Status_out You can safely ignore the above 4 signals in your ...
5369 - CrossLink: Can Lattice support MIPI CSI2 to SUBLVDS?
Currently, there is no IP supporting MIPI CSI2 to subLVDS. MIPI CSI2 to subLVDS cannot be supported due to design limitation of Crosslink product.
1759 - When using Lattice's HDMI/DVI Interface reference design, do I have to use a TMDS Level Shifter for the HDMI Transmitter interface?
Both High-Definition Multimedia Interface (HDMI) and Digital Visual Interface (DVI) adopt Transition Minimized Differential Signaling (TMDS) technology to transmit and receive data and clock over four differential links. The TMDS electrical interface ...
5244 - [LatticeECP3, LatticeECP2/M, LatticeXP2]: Is there any Lattice IP that generates On-Screen Display (OSD) with RGB888?
The 7:1 LVDS Video Interface Reference Design (RD1030) generates OSD. For reference, please refer to this direct link: http://www.latticesemi.com/view_document?document_id=21823
5176 - CrossLink: How many Clock Domains are there within a MIPI bridge design, and how to calculate it?
There are three Clock Domains within a MIPI bridge design: 1. MIPI Bit Clock Domain 2. MIPI Byte Clock Domain 3. MIPI Pixel Clock Domain The equations for calculating clock domains: 1. MIPI bit clock rate (MHz) = MIPI byte clock * 4 2. MIPI byte ...
1688 - Where can I find more information regarding the FPGA Loader reference design?
The following link provides the details description and source code for download: http://www.latticesemi.com/products/intellectualproperty/referencedesigns/parallelflashprogrammingf.cfm The FPGA Loader reference design(in the example it shows ...
5893 - CrossLink: Why is there an error when I change to 1 MIPI lane using MIPI2LVDS Reference Design?
Please try to reconfigure and regenerate the rx.sbx (rx dphy GUI), such that the number of lanes should be changed to 1 in order to be aligned with the number of lanes declared on the synthesis directives. This should address the error.
2076 - LatticeECP3: Should I run gate level simulations for the Peripheral Component Interconnect Express (PCIe) Demos from the Lattice PCIe Development kits?
It is not advisable to perform gate level simulation for the PCIe Demo designs from the PCIe Development kit. The reasons are below: There are several signals that must be forced for the link to come up. Locating these signals in the gate level ...