3571 - LatticeECP3: How to use Dphase(3:0) Dphase_sel, Dphase_lock, Rxpll_lock, Dphase_out, Rclk_out ports available in 7:1 LVDS reference design on a customized board?

3571 - LatticeECP3: How to use Dphase(3:0) Dphase_sel, Dphase_lock, Rxpll_lock, Dphase_out, Rclk_out ports available in 7:1 LVDS reference design on a customized board?

The following ports in Lattice LVDS 7:1 loopback demo are used for testing purpose to show the status of these signals to the user:
- status_out_sel,
- Status_RCLK_out,
- seven_seg,
- Status_out

You can safely ignore the above 4 signals in your custom design.

Also, there are two other signals in the reference design (dphase_sel and dphase_in) on the receiver side for the PLL.

The reference design takes the dphase_sel input to adjust the phase of the PLL manually when the dphase_in is set to 0. The PLL phase is adjusted automatically when dphase_in is set to 1.

Hence, it is up to the user to choose these two signals in their design whether to choose the RX PLL phase manually or automatically so that they can perform the required customization for their design.