1759 - When using Lattice's HDMI/DVI Interface reference design, do I have to use a TMDS Level Shifter for the HDMI Transmitter interface?

Both High-Definition Multimedia Interface (HDMI) and Digital Visual Interface (DVI) adopt Transition Minimized Differential Signaling (TMDS) technology to transmit and receive data and clock over four differential links. The TMDS electrical interface requires DC termination to 3.3V at the sink (receiver). LatticeECP2M or LatticeECP3 SERDES uses CML differential interface which is terminated to 1.2V or 1.5V. The common-mode voltage of CML is different from that of HDMI/DVI interface. An AC-coupling is required for the CML SERDES to interface the HDMI/DVI source or sink. A discrete TMDS Level Shifter can simplify the PCB design of AC-coupling interface. For example, Lattice HDMI Mezzanine Card - Revision B (http://www.latticesemi.com/documents/EB55.pdf) uses a commercial off-the-shelf AC-coupled HDMI Level Shifter STHDLS101 for the SERDES transmitter which converts CML differential signals to HDMI rev 1.3 compliant signals.

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1759 - When using Lattice's HDMI/DVI Interface reference design, do I have to use a TMDS Level Shifter for the HDMI Transmitter interface?

1759 - When using Lattice's HDMI/DVI Interface reference design, do I have to use a TMDS Level Shifter for the HDMI Transmitter interface?

Related Articles

2076 - LatticeECP3: Should I run gate level simulations for the Peripheral Component Interconnect Express (PCIe) Demos from the Lattice PCIe Development kits?

3571 - LatticeECP3: How to use Dphase(3:0) Dphase_sel, Dphase_lock, Rxpll_lock, Dphase_out, Rclk_out ports available in 7:1 LVDS reference design on a customized board?

1688 - Where can I find more information regarding the FPGA Loader reference design?

5893 - CrossLink: Why is there an error when I change to 1 MIPI lane using MIPI2LVDS Reference Design?

3630 - MachXO2: Will the command sequence implemented in the DCS ROM of the DSI TX reference design work for all displays?