SSPI
2410 - MachXO2: What will happen to the configuration ports (JTAG/I2C/SSPI) when power is removed while programming the Configuration Flash or User Flash memory?
The MachXO2 configuration ports are governed by a flash memory area, called the Feature Row. The Feature Row resides in a sector that is separate from the Configuration Flash, and User Flash Memory. The Configuration Flash or User Flash sectors must ...
2340 - [MachXO2]: What is the maximum size of the SSPI Embedded SEA/SED data files?
The SSPI Embedded data files have some overhead added to the raw data to be sent to the FPGA. At the same time the SSPI Embedded code uses a basic compression technique to try to reduce the impact of the overhead. It is difficult to determine exactly ...
2313 - LatticeXP2: Is it possible to program the LatticeXP2 SRAM directly using slave SPI mode?
Solution: No, you cannot program SRAM in SLAVE SPI(SSPI) mode. SSPI can only be utilized to program and verify an encrypted or standard JEDEC file into embedded configuration Flash in background mode. It can be used to read the SRAM fuse cells in ...
5371 - Diamond / Programmer / MachXO2: How do you communicate with MachXO2 via SSPI when it is in user mode?
Solution: More of the information about SSPI programming can be found at MachXO2 Programming and Configuration Usage Guide (TN1204). SSPI port is active when the device is in blank or erase state. However, this port is defaulted as not active or ...
5287 - Should the USRMCLK be used only when the device is in MSPI mode or if it is needed to disable the MasterSPI port to generate your own MasterSPI controller?
To enable the same SPI pins used in configuration, to User SPI, the pins need to be persistent. The user SPI control should connect the User SPI signals to those pins. The MCLK is not a GPIO pin, and can be used in User SPI. The MCLK can select ...
6003 - iCE40 Family: What are the most common causes of NVCM programming or configuration failures on iCE40 Devices?
There are 3 common causes of NVCM boot failure: 1. When NVCM programming is performed, Vpp_2V5 voltage limits have a smaller window and it should only be from 2.3V to 3,00V. 2. On some iCE40 devices such as iCE40 Ultra and iCE40 Ultraplus, there are ...
7315 - MACHXO3: Why I cannot perform SPI programming after enable dual boot to configure from external SPI flash
Description: MACHXO3 device share the same SPI SysConfig ports for both SSPI and MSPI configuration mode. The Configuration(CFG) MSPI is designed to be bus friendly, i.e. when it's not actively booting, all MSPI pins are tri-stated. It's possible to ...
2687 - MachXO2: What is best practice for the MachXO2 Slave SPI Chip Select (SN)?
The Slave SPI (SSPI) Chip Select (SN) input signal is recommended to be pulled high using an external pull-up resistor. The SSPI configuration port is the second highest in boot priority, with JTAG being the highest priority. Assertion of the SN ...
1646 - LatticeXP2: Can we program the internal SRAM via SSPI port?
No. The SSPI port can only configure the LatticeXP2 flash or read from the LatticeXP2 SRAM. The SSPI port can not write to the LatticeXP2 SRAM. The SRAM can be configured using JTAG, the external Master SPI port, or by using the data stored in ...
6984 - MachXO5-NX Development Board: How to access the MachXO5-NX Development Board via SSPI using onboard FTDI?
To access the MachXO5-NX Development Board via SSPI using the onboard FTDI, the user should follow the steps as described below. 1.) The MachXO5-NX Development Board Setup is shown below.
6194 - All Nexus: Is it possible to program the device without connecting the MISO signal?
Yes it is possible, you just need to modify the programming flow such that only Class B, C, and D commands are used. Referring to the original slave SPI configuration flow (Figure 6.9). The following should be considered: Skip steps 2 and 3 (READ ID) ...
5811 - iCE40 LP: The NVCM programming spec frequently mentions wait times equivalent to a certain number of clock cycles even if SPI_SS_B pin is high. Does the master need to provide actual clocks in the SPI_SCK pin during these wait times?
The master needs to provide clock pulses during those wait times where SPI_SS_B is high. Customers should be aware of this and they should incorporate this into their microcontroller firmware. The recent version of the NVCM programming specs ...
5786 - iCE40 LP: Is daisy-chain programming possible on multiple iCE40 chips?
iCE40 does not support daisy chain programming. However, since programming is through SPI interface, SPI_SO, SPI_SI, SPI_SCK, and CRESET_B pins can still be connected on the same bus. SPI_SS pins should be separated which are controlled by the ...
5779 - iCE40 UltraPlus: Can iCE40 devices be configured in Master SPI or Slave SPI mode if the NVCM has already been programmed?
When the NVCM of an iCE40 device has already been programmed, it can no longer be configured in Master SPI mode (SPI serial Flash PROM). However, Slave SPI is still possible which could be an external device, such as a processor, microcontroller, or ...
6954 - All Nexus Families: How are the commands and bitstream sent in the Nexus device via Quad (x4) Slave SPI?
See below on how to send the commands in Quad (x4) SSPI mode in comparison to Standard(x1) SSPI mode 1.) See below comparison on how the commands are sent using Standard Slave SPI vs. Quad Slave SPI. In this example, the LSC_REFRESH (0x79) command ...
1974 - LatticeXP2: Why are padding bits required for every LatticeXP2 FPGA except the LatticeXP2-40 when it is programmed in Slave SPI mode?
The LatticeXP2 configuration memory is arranged in an array. The array size varies depending on the number of logic elements available in the FPGA. The LatticeXP2 array dimensions are as follows: LatticeXP2-5: 1938 rows, each 638 bits wide ...
5618 - iCE40: Is it possible to boot from an External Flash if the iCE40 device is already programmed in NVCM mode?
Once the device is programmed in NVCM mode, you will no longer be able to boot from an external Flash. However, you can still configure directly to the SRAM through an external SPI Master such as a Microcontroller. Please refer to FPGA-TN-02001 for ...