5811 - iCE40 LP: The NVCM programming spec frequently mentions wait times equivalent to a certain number of clock cycles even if SPI_SS_B pin is high. Does the master need to provide actual clocks in the SPI_SCK pin during these wait times?
The master needs to provide clock pulses during those wait times where SPI_SS_B is high. Customers should be aware of this and they should incorporate this into their microcontroller firmware. The recent version of the NVCM programming specs explained better since there is a separate column for the number of clock pulses that need to be provided.
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