3916 - MachXO3: Can we overwrite the outdated design pre-programmed into Non-Volatile Configuration Memory (NVCM) by re-configuring the SRAM fabric of the MachXO3 through one of the programming ports like SPI/I2C/JTAG?

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• 3756 - iCE40: What is the effect of setting the security bit in iCE40 devices? How to verify if the security bit is set? If the security bit is not set, how to read the Non-Volatile Configuration Memory (NVCM) data?

  It is not possible to obtain the data if Non-Volatile Configuration Memory (NVCM) is programmed with the security feature for iCE40. The security feature of the iCE40 device permanently disables any reading of NVCM data from the device. To verify if ...

• 2410 - MachXO2: What will happen to the configuration ports (JTAG/I2C/SSPI) when power is removed while programming the Configuration Flash or User Flash memory?

  The MachXO2 configuration ports are governed by a flash memory area, called the Feature Row. The Feature Row resides in a sector that is separate from the Configuration Flash, and User Flash Memory. The Configuration Flash or User Flash sectors must ...

• 1422 - Can I configure the configuration SRAM memory with the Slave SPI Mode(SSPI)?

  You can not configure the configuration SRAM memory directly with the Slave SPI Mode(SSPI), nor can you read back SRAM memory with the SSPI. But you can use the SSPI to configure the SRAM memory through a REFRESH instruction. The effect is the same ...

• 1943 - MachXO: With no DONE bit, how can I use JTAG to see if the SRAM download from flash is finished?

  The way to check the MachXO configuration status through JTAG is to use the capture instruction. For the MachXO the capture instruction (which is the instruction shifting out of the instruction register) is 0x19 (if the device is blank) or 0x1D (if ...

• 103 - Can the LatticeXP2 use encrypted configuration bitstreams supplied by an external SPI Master or SPI Slave?

  The LatticeXP2 provides two methods to supply non-volatile programming images into the FPGA configuration memory. The first method employs an on-chip flash memory that is read and loaded at power-up or image refresh. The second method allows an ...