2687 - MachXO2: What is best practice for the MachXO2 Slave SPI Chip Select <b>(SN)</b>?

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• How to enable SSPI programming in MachX03-9400 Development Board

  To enable SSPI programming, this is the generic checklist user should follow through: Enable SPI port in Diamond/Radiant Software Tools some device may have Slave SPI port enabled, but it is essential for user to cross-check their project to ensure ...

• 1974 - LatticeXP2: Why are padding bits required for every LatticeXP2 FPGA <b>except</b> the LatticeXP2-40 when it is programmed in Slave SPI mode?

  The LatticeXP2 configuration memory is arranged in an array. The array size varies depending on the number of logic elements available in the FPGA. The LatticeXP2 array dimensions are as follows: LatticeXP2-5: 1938 rows, each 638 bits wide ...

• 103 - Can the LatticeXP2 use encrypted configuration bitstreams supplied by an external SPI Master or SPI Slave?

  The LatticeXP2 provides two methods to supply non-volatile programming images into the FPGA configuration memory. The first method employs an on-chip flash memory that is read and loaded at power-up or image refresh. The second method allows an ...

• 2313 - LatticeXP2: Is it possible to program the LatticeXP2 SRAM directly using slave SPI mode?

  Solution: No, you cannot program SRAM in SLAVE SPI(SSPI) mode. SSPI can only be utilized to program and verify an encrypted or standard JEDEC file into embedded configuration Flash in background mode. It can be used to read the SRAM fuse cells in ...

• 6954 - All Nexus Families: How are the commands and bitstream sent in the Nexus device via Quad (x4) Slave SPI?

  See below on how to send the commands in Quad (x4) SSPI mode in comparison to Standard(x1) SSPI mode 1.) See below comparison on how the commands are sent using Standard Slave SPI vs. Quad Slave SPI. In this example, the LSC_REFRESH (0x79) command ...