This article clarifies the clock domain assignments for the MII/GMII interface as described in the Tri-Speed Ethernet IP User Guide (FPGA-IPUG-02084-2.2). The table below includes an amended version of the original documentation to help users ...
Yes, when the received frame length exceeds the max_frame_len register setting, the Receiver of Tri-speed MAC block can still receive the frame correctly. But need to set the flag of rx_stat_vector[31], indicating it’s a long frame, and there is no ...
Description: Following error is encountered when compiling Radiant project with Tri-speed Ethernet MAC IP version 1.4.0, which is due to invalid .ldc file constraint: Error 1026000 Synthesis ERROR - ...
Lattice Technical Support Expectation Please be advised that highest priority for Lattice Technical Support will be given to 1. Software which is not working as expected or suspected bugs. We recommend that customers use the latest software tools and ...
Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...
Glitch Fliter is used to prevent short-duration events of glitches, This is used to prevent False tripping on noise in a system. GLITCHFilter in device constraints , enables 1ns glitch filtering.
Description: Nexus device family has a default I2C slave address of 0x40 and you are allow to modify it based on your requirement. Solution: To permanently modify the I2C address, you can modify the desired value in .fea file and use the Programmer ...
Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo.