3051 - LatticeECP5: When the packet size is larger than the value defined in Maximum Packet Size register, can Tri-speed MAC block still work?

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• 3524 - Lattice ECP3: How can we access configuration registers of Lattice Tri-Speed Ethernet MAC (TSMAC) IP Core ?

  Configuration registers of Tri-Speed Ethernet MAC (TSMAC) IP Core can be accessed through Host Interface. Also, values for particular registers can be hard coded in the ts_mac_core.v file if you are not using any host interface module in your design.

• 6968 - Tri-speed Ethernet MAC: How to resolve Tri-speed Ethernet MAC version 1.4.0 synthesis error?

  Description: Following error is encountered when compiling Radiant project with Tri-speed Ethernet MAC IP version 1.4.0, which is due to invalid .ldc file constraint: Error 1026000 Synthesis ERROR - ...

• 2545 - LatticeECP3: Why does the SGMII and Gb Ethernet PCS IP reduce the Inter Packet Gap between Ethernet frames?

  Description:The Inter Packet Gap (IPG) shrink (deleting of /I2/ ordered set) will always happens as long as there is a PPM (Part per Million) difference between the local reference clock and the remote reference clock, and the remote reference clock ...

• 1514 - LatticeSC/M: What effect does a PCS local/remote fault signal to the 10Gb+ Ethernet MAC have on the MAC TX and RX logic?

  Description: The XAUI PCS communicates the local/remote link fault to the MAC via the XGMII RX data/control bus during the IDLE period, as defined by the IEEE specification. No other signals are used to communicate fault signaling. When the RX MAC ...

• 1991 - SGMII and Gb Ethernet PCS IP Core: How many idle ordered sets will the IP's Clock Tolerance Compensation logic insert or delete during an inter-packet gap period?

  The Clock Tolerance Compensation (CTC) logic in the SGMII and Gb Ethernet PCS IP Core performs both idle ordered set insertion when the CTC FIFO low watemark is reached and idle ordered set deletion when the CTC FIFO high watemark is reached. CTC ...