DisplayPort
DisplayPort IP RX Intermittent Interlane Alignment Loss of Lock for TPS2
Description: When TPS2 is used during link training, intermittent occurrences have been observed where the DisplayPort IP internal deskew logic latches onto an incorrect test pattern alignment and is unable to recover. As a result, the DisplayPort IP ...
Overlapping BS Between Idle to Active Video Stream Transition
Description: There is a known issue where the BS (Blanking Start) of the idle pattern, which occurs at every 8192th symbol, overlaps with the BS of the active video stream during transition from idle to active mode. This overlap causes the IP to ...
DisplayPort IP RX 8.1G Unable to Achieve Interlane Alignment
Description: DisplayPort IP(RX) operating at 8.1 Gbps may encounter an issue where the DisplayPort IP is unable to achieve interlane alignment during link training. This is due to some hardware have lane data arrives earlier than expected, resulting ...
DisplayPort RX IP does not support backpressure
Description: DisplayPort RX IP does not support backpressure. The IP continues to output data even when the downstream tready signal is deasserted. Resolution: A shallow buffer will be introduced in a future IP release to handle occasional tready ...
DisplayPort IP symbol Transfer Unit (TU) size is capped at 63
Description: The DisplayPort IP TU size is capped at 63 to avoid link oversubscription. Resolution: Users are required to increase to a higher link rate or lane count to avoid hitting the maximum 64-symbol TU. Users may refer to "Valid Bytes per TU" ...
DisplayPort TX IP link training sequence not compliant with the DisplayPort Specification
Description: The DisplayPort IP link training sequence is a subset of the DisplayPort Specification and does not yet support voltage and pre-emphasis adjustment requests, link rate down-training, or lane count down-training. Resolution: This will be ...
DisplayPort TX IP unable to handle I2C_DEFER and I2C_NACK
Description: The DisplayPort IP is not able to respond to I2C_DEFER and I2C_NACK correctly. Resolution: This will be fixed in the next DisplayPort IP release.
DisplayPort IP resolutions must be divisible by 4
Description: The DisplayPort IP may not be able to handle custom resolutions that are not divisible by 4 (i.e., 1366x768). This applies to both the RX and TX of DisplayPort IP. Resolution: This will be fixed in the next DisplayPort IP release.
DisplayPort TX IP AUX_CH fails to retry on NACK for an AUX_WR transaction
Description: The DisplayPort TX IP does not retry after a NACK response to an AUX write transaction. Resolution: This will be fixed in the next DisplayPort IP release.
DisplayPort RX IP AUX channel does not handle I2C write at the end of a transaction (MOT=0)
Description: The DisplayPort IP does not return I2C_ACK when receiving the end-of-transaction MOT=0, so it cannot correctly close the I2C transaction. Resolution: This will be fixed in the next DisplayPort IP release.
DisplayPort RX IP returns AUX_ACK instead of AUX_NACK when writing to an unsupported DPCD address
Description: The DisplayPort IP generates an illegal response to an AUX request when accessing a reserved DPCD address. The DisplayPort RX IP should return AUX_NACK when writing to an unsupported DPCD address, but the design responds with AUX_ACK. ...
DisplayPort TX IP Version 2.1.0 does not support back-to-back video input without blanking interval
Description DisplayPort TX IP version 2.1.0 requires the video input to provide blanking interval between active horizontal video lines to ensure correct video data packing. Failure symptoms include no video image output or black screen, even though ...
5815 - [CrossLink] In DSI to RGB, why is it that HSYNC and VSYNC are not asserted?
DPHY to CMOS soft IP is looking for data type -- VSYNC_END = 11h -- in the signal whereas from the FPD-to-DSI, it does not provide. Reviewing the implementations, MIPI DPHY-to-CMOS supports non-burst mode with sync pulses while FPD-link-to-DSI ...