DisplayPort IP RX Intermittent Interlane Alignment Loss of Lock for TPS2

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• DisplayPort IP RX 8.1G Unable to Achieve Interlane Alignment

  Description: DisplayPort IP(RX) operating at 8.1 Gbps may encounter an issue where the DisplayPort IP is unable to achieve interlane alignment during link training. This is due to some hardware have lane data arrives earlier than expected, resulting ...

• DisplayPort RX IP does not support backpressure

  Description: DisplayPort RX IP does not support backpressure. The IP continues to output data even when the downstream tready signal is deasserted. Resolution: A shallow buffer will be introduced in a future IP release to handle occasional tready ...

• DisplayPort IP resolutions must be divisible by 4

  Description: The DisplayPort IP may not be able to handle custom resolutions that are not divisible by 4 (i.e., 1366x768). This applies to both the RX and TX of DisplayPort IP. Resolution: This will be fixed in the next DisplayPort IP release.

• DisplayPort RX IP returns AUX_ACK instead of AUX_NACK when writing to an unsupported DPCD address

  Description: The DisplayPort IP generates an illegal response to an AUX request when accessing a reserved DPCD address. The DisplayPort RX IP should return AUX_NACK when writing to an unsupported DPCD address, but the design responds with AUX_ACK. ...

• DisplayPort RX IP AUX channel does not handle I2C write at the end of a transaction (MOT=0)

  Description: The DisplayPort IP does not return I2C_ACK when receiving the end-of-transaction MOT=0, so it cannot correctly close the I2C transaction. Resolution: This will be fixed in the next DisplayPort IP release.