5815 - [CrossLink] In DSI to RGB, why is it that HSYNC and VSYNC are not asserted?

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• 6324 - B2P for CrossLink: What are the specific values

  Data type for the following is as follows: VSYNC_START = 6'h01; VSYNC_END = 6'h11; HSYNC_START = 6'h21; HSYNC_END = 6'h31;

• 5775 - [CrossLink] [MIPI DSI Display Interface Bandwidth Reducer IP]: How many lanes can be set to configure the 1:2 MIPI DSI bandwidth reducer IP single lane?

  Please refer to the FPGA-IPUG-02028 document, otherwise known as 1:2 MIPI DSI Display Interface Bandwidth Reducer IP. Table 3.1 shows that the number of lanes is fixed to 4 and non-configurable.

• 5879 - CrossLink: How to configure the Reference Design MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for DSI single lane?<div><br></div>

  Please refer to FPGA-RD-02060 Section 3, Design and Module Description. On the project file, modify the rx_dphy which is declared under rx/rx.sbx. On the Receiver section of the IP, modify the RX Interface to DSI and the Number of RX Lanes to one.

• 5389 - CrossLink: Why does the generated VHDL code does not contain any ports for CSI2/DSI D-Phy Receiver IP?

  Description: CSI2/DSI D-Phy is a submodule IP. This only provides an instantiation templates for vhdl because it is expected that it will be used in a larger design. In addition, generating this IP is done in Verilog.

• 6472 - Crosslink: Can I use FPGA chips of the CrossLink series to organize a bridge MIPI DSI to MIPI CSI-2?

  For your application needs, there is a Reference Design that you can try which is 1 to N MIPI CSI-2/DSI Duplicator. Please refer to the webpage and documentation is also provided: ...