The CrossLink-NX family supports a maximum of 4 virtual channels (VCs) per D-PHY interface when using standard configuration. This limit applies to both hard and soft D-PHY instances, ensuring consistent performance and timing closure across ...
In Crosslink IP, Lattice do not have color bar pattern generator except for cmos-to-dphy IP but you may try to check MIPI CSI-2 Transmit Bridge Reference Design for other Lattice FPGA devices. Here's the link: ...
Our CMOS to DPHY IP expects explicit syncs from the upstream device. From the BT.1120 spec, it looks like it send EAV & SAV code which has the embedded sync information. Our existing IP cannot support this. To support BT.1120, the customer would need ...