In Crosslink IP, Lattice do not have color bar pattern generator except for cmos-to-dphy IP but you may try to check MIPI CSI-2 Transmit Bridge Reference Design for other Lattice FPGA devices. Here's the link: ...
Our CMOS to DPHY IP expects explicit syncs from the upstream device. From the BT.1120 spec, it looks like it send EAV & SAV code which has the embedded sync information. Our existing IP cannot support this. To support BT.1120, the customer would need ...
Description: This FAQ explains why Hard D-PHY blocks cannot be configured for more than 4 lanes in CrossLink product. Solution: In CrossLink product, there are 2x 4-lane D-PHY. Each of the 4-lane D-PHY runs on its own clock and has its own clock ...