The CrossLink-NX family supports a maximum of 4 virtual channels (VCs) per D-PHY interface when using standard configuration. This limit applies to both hard and soft D-PHY instances, ensuring consistent performance and timing closure across ...
In Crosslink IP, Lattice do not have color bar pattern generator except for cmos-to-dphy IP but you may try to check MIPI CSI-2 Transmit Bridge Reference Design for other Lattice FPGA devices. Here's the link: ...
Description: This FAQ explains why Hard D-PHY blocks cannot be configured for more than 4 lanes in CrossLink product. Solution: In CrossLink product, there are 2x 4-lane D-PHY. Each of the 4-lane D-PHY runs on its own clock and has its own clock ...