5642 - Crosslink : Can the Crosslink support ITU BT.1120?

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  LatticeECP3 has SERDES block that can run in simple 8-bit-only mode to support SDH/SONET (Synchronous Digital Hierarchy/ Synchronous Optical Networking) framer and mapper applications. System requirement might provide some flexibility. There are ...

• 6458 - CrossLink-NX: Why does I2C Master Core IP does not have documentation about I2C repeated start?

  Description: The I2C Master IP from Lattice does not support repeated start to allow a read then write or a write then read command. Solution: A workaround for this is to perform separate start-stop transactions, refer to FPGA-IPUG-02071 section 2.5. ...

• 7743 - How to implement Gigabit Ethernet in Certus-NX, CertusPro-NX, MachXO5-NX and CrossLink-NX FPGAs?

  Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...

• 1061 - Lattice All FPGAs: Which device is the minimal device needed to support PCI Express x1 and x4 core?

  The PCI Express x1 and x4 IP Core is supported by both SC and ECP2 device families. The minimal ECP2M device needed to support the core is LFE2M-20E-6F484C, and the minimal SC device needed is LFSC3GA15E-6F900C. Newer Lattice FPGA families that ...

• 6114 - Crosslink NX : Are there any Reference Designs of DPHY for different applications as stated below? 1. Connecting Soft DPHY Rx module output to Soft DPHY Tx module input. 2. Image acquisition from a camera through Hard DPHY.

  Solution: The following RDs available for Crosslink-NX will support the said applications: 1. FPGA-RD-02212 : N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation - Aggregate multiple Image Sensors into a single Output with Minimal Latency. - Uses ...