5775 - [CrossLink] [MIPI DSI Display Interface Bandwidth Reducer IP]: How many lanes can be set to configure the 1:2 MIPI DSI bandwidth reducer IP single lane?

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• 5879 - CrossLink: How to configure the Reference Design MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for DSI single lane?<div><br></div>

  Please refer to FPGA-RD-02060 Section 3, Design and Module Description. On the project file, modify the rx_dphy which is declared under rx/rx.sbx. On the Receiver section of the IP, modify the RX Interface to DSI and the Number of RX Lanes to one.

• 5711 - FPDLink to DSI 1.2:&nbsp; OpenLDI to DSI IP seems to support on VESA mapping of the incoming OpenLDI datastream. Does this IP support the JEIDA mapping? In case it does not, how can we implement this functionality?

  The difference between VESA and JEIDA mapping looks like the arrangement of the sequence of signals. In the Verilog file generated under fdp_link_2_dsi which is located in the rtl folder, you may want to reconfigure the arrangement based on JEIDA ...

• 5923 - MIPI D-PHY to CMOS Interface Bridge Soft IP: Can the DSI to CMOS IP be changed to DPHY1 from DPHY0?

  The user can change the hardened D-PHY blocks location between DPHY0 and DPHY1 by adding a LOCATE preference in the .lpf file to SITE "MIPIDPHY0" or SITE "MIPIDPHY1". The LOCATE preference is the following, for example: LOCATE COMP " ...

• 5691 - Crosslink / CSI-2/DSI D-PHY Transmitter IP Core : For Crosslink, how can I get the register value from the display(destination)?

  DSI-TX IP is only capable of transmission only and do not support bus turn around. This means, it does not support read type of "DCS" command in HS-mode / LP-mode.

• 6798 - MIPI for CertusPro-NX/CrossLink-NX: What is the maximum CSI RX Bandwidth?

  Please refer to aggregated bandwidth: CertusPro-NX: (softIP: sysIOx3 banks ==> 1.5Gbps 4lane x 3 ports ==> 18Gbps) Crosslink-NX: (hardIP: 2 ports ==> 2.5Gbps 4lane x 2 ports ==> 20Gbps) + softIP ==> (total 38Gbps)