Interface & Protocol IPs | Byte To Pixel

Byte to Pixel
7681 - Pixel-to-Byte IP v1.7.0: Why do I encounter interruption on the MIPI long packet transmission after a while when connecting lp_en_o from P2B v1.7.0 to lp_en_i of DPHY_TX? However, when I delay the lp_en_o by one clock and then connect to DPHY TX,
The lp_en flag needs to be delayed depending on the data type / number of pixel lanes. User would need to fine tune between the lp_en_o and lp_en_i to get the correct transmission.
3624 - LatticeECP3: What are the supported rates for Mobile Industry Processor Interface (MIPI) Camera Serial Interface (CSI) on Lattice ECP3?
The supported rates for the MIPI CSI RX and TX on Lattice ECP3 -8 speed grade are 550 Mbps and 756 Mbps respectively.
6396 - Byte-to-Pixel IP v1.4.0: Why are there no exception constraints between the byte clock and pixel clock, e.g. set_clock_groups constraints for each clock in the IP LDC file?
The set_clock_groups or any exception constraints were not defined in the IP LDC file as it would be difficult if the IP is used in a system design and the customer wants to analyze the paths between the clocks or does not want the clock domain ...
6324 - B2P for CrossLink: What are the specific values
Data type for the following is as follows: VSYNC_START = 6'h01; VSYNC_END = 6'h11; HSYNC_START = 6'h21; HSYNC_END = 6'h31;
6321 - CrossLink-NX: Why are there no exception constraints between the byte clock and pixel clock, e.g. set_clock_groups constraints for each clock in the IP LDC file?
The set_clock_groups or any exception constraints were not defined in the IP LDC file as it would be difficult if the IP is used in a system design and the customer wants to analyze the paths between the clocks or does not want the clock domain ...
5924 - D-PHY to CMOS v1.2/CrossLink: Why does the DPHY RX channel signal did not move from LP to HS mode?
This is due to metastability encountered in v1.2. It is recommended to upgrade to DPHY to CMOS v1.3 with the corresponding IP fix.
4207 - [iCE40 LP/HX] Does iCE40 supports implementation of 7:1 LVDS display interface?
Feasibility analysis has not been done on iCE40 hence Lattice recommends to use MachXO2 for the implementation of 7:1 LVDS display interface.
6199 - Byte to Pixel of CrossLink: Does the output data valid when lv_o becomes high?
The pd_o outputs as soon as the lv_o is asserted high. So, within lv_o high assertions, data are valid.

Interface & Protocol IPs | Byte To Pixel | Knowledge Base

Byte to Pixel

7681 - Pixel-to-Byte IP v1.7.0: Why do I encounter interruption on the MIPI long packet transmission after a while when connecting lp_en_o from P2B v1.7.0 to lp_en_i of DPHY_TX? However, when I delay the lp_en_o by one clock and then connect to DPHY TX,

3624 - LatticeECP3: What are the supported rates for Mobile Industry Processor Interface (MIPI) Camera Serial Interface (CSI) on Lattice ECP3?

6396 - Byte-to-Pixel IP v1.4.0: Why are there no exception constraints between the byte clock and pixel clock, e.g. set_clock_groups constraints for each clock in the IP LDC file?

6324 - B2P for CrossLink: What are the specific values

6321 - CrossLink-NX: Why are there no exception constraints between the byte clock and pixel clock, e.g. set_clock_groups constraints for each clock in the IP LDC file?

5924 - D-PHY to CMOS v1.2/CrossLink: Why does the DPHY RX channel signal did not move from LP to HS mode?

4207 - [iCE40 LP/HX] Does iCE40 supports implementation of 7:1 LVDS display interface?

6199 - Byte to Pixel of CrossLink: Does the output data valid when lv_o becomes high?