FPGA Software & Tools (Diamond / Radiant / ICEcube2 / IspLEVER Classic) | Pre Synthesis / Post-Synthesis Timing Constraints Editor

Pre Synthesis / Post-Synthesis Timing Constraints Editor
4072 - Diamond 3.3 / MachXO2: How can a user constraint Place & Route (PAR) for the MachXO2 built in oscillator to cover the 5% frequency tolerance variation?
Description: In Lattice Diamond 3.3 and later, PAR will accept a frequency constraint up to 5.5% above the nominal frequency setting to cover the timing variation in the oscillator over PVT. This can be done by adding a constraint in the Lattice ...
7236 - create_clock on a clock inside a PCIe/SERDES IP is ignored after synthesis in Radiant 2022.1
Symptom A create_clock constraint applied in a Synplify Pro .fdc file to a clock pin inside a PCIe or SERDES IP passes the synthesis constraint check, but has no effect afterwards. The post-synthesis log reports: WARNING - No pin matched ...
7378 - All FPGA: What does the inferred clock warning "WARNING <2019993> - MT420 |Found inferred clock...with period...Please declare a user-defined clock on..."?
Description: WARNING <2019993> - MT420 |Found inferred clock cpu_pll_ipgen_lscc_pll_Z21_layer0|clkop_o_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net cpu_system_i.cpu_pll_i.lscc_pll_inst.clk_50M. Solution: The ...
6529 - All FPGA: Why does PLL outputs' constraints does not propagate from ldc/fdc/sdc to Synthesis using both SynplifyPro & LSE?
Description: Lattice Diamond software does not use any pre-synthesis constraint file (SDC/LDC/FDC). Solution: There is a workaround to compensate for the limitation. Once the user has created any pre-synthesis constraint file, synthesize the design ...
6488 - All Devices: Why does 'set_multicycle_path -hold' constraint is not propagated to Synthesis using Synplify Pro FDC file?
Description: The issue is present using Radiant 3.1.1 or below on any of the available FPGA devices on the tool. Solution: There is a work around using the Tcl console in the radiant GUI, or if you opt to use the tool from the command line it is even ...

FPGA Software & Tools (Diamond / Radiant / ICEcube2 / IspLEVER Classic) | Pre Synthesis / Post-Synthesis Timing Constraints Editor | Knowledge Base

Pre Synthesis / Post-Synthesis Timing Constraints Editor

4072 - Diamond 3.3 / MachXO2: How can a user constraint Place &amp; Route (PAR) for the MachXO2 built in oscillator to cover the 5% frequency tolerance variation?

7236 - create_clock on a clock inside a PCIe/SERDES IP is ignored after synthesis in Radiant 2022.1

7378 - All FPGA: What does the inferred clock warning "WARNING <2019993> - MT420 |Found inferred clock...with period...Please declare a user-defined clock on..."?

6529 - All FPGA: Why does PLL outputs' constraints does not propagate from ldc/fdc/sdc to Synthesis using both SynplifyPro &amp; LSE?

6488 - All Devices: Why does 'set_multicycle_path -hold' constraint is not propagated to Synthesis using Synplify Pro FDC file?

4072 - Diamond 3.3 / MachXO2: How can a user constraint Place & Route (PAR) for the MachXO2 built in oscillator to cover the 5% frequency tolerance variation?

6529 - All FPGA: Why does PLL outputs' constraints does not propagate from ldc/fdc/sdc to Synthesis using both SynplifyPro & LSE?