Description:

In Lattice Diamond 3.3 and later, PAR will accept a frequency constraint up to 5.5% above the nominal frequency setting to cover the timing variation in the oscillator over PVT. This can be done by adding a constraint in the Lattice Preference File (*.lpf file) which will override the internal oscillator's frequency defined in the HDL.

Solution: 

Lets say the internal oscillator frequency is 53.2MHz, and adding 5% tolerance, the frequency would be 55.86MHz.

In order for the PAR to generate timing report at 55.86MHz, or at 56MHz (which is within 5.5% tolerance, as allowed by the tool), include the following constraint in the .lpf file;

FREQUENCY NET "osc_clk" 56 MHz ;

The "osc_clk" mentioned in the above constraint is the internal oscillator's clock-net name. 

Once the PAR process is done, check the PAR TRACE report. You will find the timing report generated for 56MHz.

For Diamond 3.2 and before, the workaround is to use the next available higher frequency value from MachXO2 sysCLOCK PLL Design and Usage Guide (TN1199), Table 13-15, OSCH Supported Frequency Settings, PAR TRACE will use that to create the timing reports for the design.

For example:

Lets consider the same example as above, the internal oscillator's frequency is 53.2MHz, and adding 5% tolerance, 

the frequency would be 55.86MHz. The next higher valid frequency value from TN1199, Table 13-15, is 66.50MHz. 

Hence, in order to accommodate 5% tolerance, add the following constraint in your .lpf file;

FREQUENCY NET "osc_clk" 66.50 MHz ;

User should now be able to see that the timing report is generated for 66.50MHz.