All Devices: Why does 'set_multicycle_path -hold' constraint is not propagated to Synthesis using Synplify Pro FDC file?
Description:
The issue is present using Radiant 3.1.1 or below on any of the available FPGA devices on the tool.
Solution:
There is a work around using the Tcl console in the radiant GUI, or if you opt to use the tool from the command line it is even simpler.
1. Run synthesis as normal (checking the *impl_1.tws file now shows that the constraint with -hold was dropped.
2. Edit the *impl_1.ldc file (should say written by Synplify-Pro at the top of the file) in the following ways:
- uncomment the constraint with the -hold option
- copy paste the -from and -to object lists from the -setup constraint to the -hold constraint
3. Use the tcl console (from Radiant GUI or command line) to run the following commands (Note: I have shortened the file paths to make it more readable, user will have to find correct paths.):
- postsyn -a LFCPNX -p LFCPNX-100 -t BBG484 -sp 7_High-Performance_1.0V -oc Industrial -top -w -o board_ctrl_impl_1_syn.udb -ldc impl_1/*impl_1.ldc -gui -msgset promote.xml impl_1/*impl_1.vm
- timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -html -rpt "*impl_1.tws" "*impl_1_syn.udb"
4. Open the *impl_1.tws file (ex: *impl_1_css.tw1.html) and see that the constraint is now reported. (Note that it may not update in the GUI report tab and should be viewed in a separate text editor)