Radiant 2023.1: Why is the 'create_clock' constraint excluded from FDC?

Description:

After evaluating the fix in Radiant 2022.1 for DNG-15807, the create_clock constraint in *.fdc still persists, and upon checking, the design has an unmatched constrained object in *.ldc and *.vm in which the mismatch happens before post-synthesis in Synplify Pro.

Solution:

This is a known bug, and it is fixed starting with Radiant 2023.2 or later.

• Related Articles

• Radiant: When to use a create_clock or create_generated_clock constraint? What are the consequences if a create_clock constraint is used instead of a create_generated_clock constraint?

  Use create_clock constraints when the clock is coming from an input port. Use create_generated_clock constraints when the clock is generated from a module or circuit inside the FPGA design through multiplication or division of a base clock. The ...

• How can the user set a false path on my pre-synthesis constraint files (SDC/FDC) between the PLL clock outputs if these are generated in the post-synthesis stage?

  To set this as false_path in pre-synthesis, user need to define the create_generated_clock on the SDC/FDC file as well. Just make sure that the create_generated_clock constraint at the pre-synthesis stage captures all of the properties of the PLL ...

• Lattice Radiant / PLL: What compilation process or stage does the software automatically define the create_generated_clock constraints of the PLL clock outputs? Can the user use the generated clocks on other constraints define in the pre-synthesis stage (e.g. set_clock_groups, etc.)?

  Any clock output of the PLL has an automatically create_generated_clock constraint defined in the post-synthesis stage. Thus, user can use the generated clocks on their constraints as long as they are using post-synthesis constraints. If the user ...

• All FPGA: Why does PLL outputs' constraints does not propagate from ldc/fdc/sdc to Synthesis using both SynplifyPro & LSE?

  Description: Lattice Diamond software does not use any pre-synthesis constraint file (SDC/LDC/FDC). Solution: There is a workaround to compensate for the limitation. Once the user has created any pre-synthesis constraint file, synthesize the design ...

• All Devices: Why does 'set_multicycle_path -hold' constraint is not propagated to Synthesis using Synplify Pro FDC file?

  Description: The issue is present using Radiant 3.1.1 or below on any of the available FPGA devices on the tool. Solution: There is a work around using the Tcl console in the radiant GUI, or if you opt to use the tool from the command line it is even ...