Logic Blocks (LUTs, Registers)
204 - All FPGA: What is the initial logic level of a register after power-up?
Definition: We will consider two cases: (1) the control (reset, set) and clock signals are active upon device power-up and (2) the control and clock signals are in-active upon power-up. Solution: In the first case, the register's output will be ...
2240 - MachXO2: Why does my XO2 EFB SPI / I2C Interface Lock Up when operating as a slave?
This scenario is encountered when using the EFB as an I2C or SPI slave interface. Data stops being recieved when the Receive Data Register (RXDR) for the SPI or I2C becomes full. In order to prevent overwriting data, the XO2 EFB will store data bits ...
6083 - What is the difference of PFU and Logic Cells?
A PFU is not the same as a Logic Cell. Logic Cells are an arbitrary count that is a composite number of LUT’s, Registers, RAM, and DSPs. Whereas, PFUs are actual counts of LUTs and Registers.
2794 - ECP5: What's the propagation delay inside LUTs of Lattice ECP3?
The SLICE is the basic logic unit of LatticeECP3 devices, each SLICE contains two LUT4s. A/B/C/D are input ports of LUT, FCI is input port of carry chain, F is output port of LUT4, OFX is output port of LUT6, and FCO is output port of carry chain. ...
6651 - DELAYF of ECP5/ECP5-5G
The minimum width check for LOADN/MOVE/DIRECTION signal is 2,500 ps. The delay setting is effective only after minimum time of 810 ps after the falling edge of MOVE signal.
3878 - iCE40: What is the state of flip-flops during Power On Reset (POR) in iCE40 devices?
The global reset control signal connects to all Programmable Logic Blocks (PLBs) and Programmable Inputs/Outputs (PIOs) flip-flops on the iCE40 device. The global reset signal is automatically asserted throughout the configuration process, forcing ...
3812 - How to find the number of gates available for a Lattice device?
Lattice does not have any data regarding the gate counts for a device. Only the Look-Up Table (LUT) counts are available for a device. The reason is that an LUT can be configured in an end design either as INVERTER or 4 input AND gate. The actual ...