This scenario is encountered when using the EFB as an I2C or SPI slave interface. Data stops being recieved when the Receive Data Register (RXDR) for the SPI or I2C becomes full. In order to prevent overwriting data, the XO2 EFB will store data bits in two 8-bit registers until it becomes full. The EFB SPI / I2C interface will then hold the bus until the user logic reads the RX Data Register (RXDR) before it allows more data to be received.
In order to prevent this from happening the user must ensure to setup the interrupt register. Then, when an interrupt is received, you must read the RXDR, then reset the interrupt and data will continue flowing.
For other detailed information on the hardened XO2 EFB interfaces please reference TN1205 PDF.