Basic & Foundational IPs | FIFO_DC

FIFO_DC
235 - All FPGA: How does the output register and read enable (RDEN) signal affect Dual Clock FIFO (FIFO_DC)?
Description: The IPexpress tool within Lattice development software allows user to generate FIFO_DC using Embedded Block Ram (EBR) or distributed memory. During the generation of the FIFO_DC module, there are options to use output registers, and/or ...
6418 - FIFO for Nexus FPGAs: How does the three FIFO_DC Controller Implementation differs from each other?
1. Controller Implementation = Area-Optimized (HW): Uses a Hardened FIFO controller + Hardened Memory Block for data storage. 2. Controller Implementation =Feature-Rich (LUT) ; Implementation type = EBR: Uses a Fabric-implemented FIFO controller + ...
7146 - FIFO_DC IP: Does the LSCC_FIFO_DC have First Word Fall Through(FWFT) feature?
The FWFT feature is only available to Avant through version 2.0.0; which is still separated from the Nexus FIFOs (which is currently version 1.4.0).
2095 - LatticeECP3: How does the Big/Little Endian switch mode affects the functionality of the FIFO DC?
The Big/Little Endian mode switch will affect the word order when read data bus width and write data bus width are set as different values: Case 1: write data bus width is 36bits and read data bus width is 18bits For the Big Endian mode: if write ...
6691 - FIFO_DC IP (Radiant 2023.2 and earlier): How to resolve hold timing violation using the recommended FIFO_DC post-synthesis constraint?
Description: The result for the hold analysis report is not what we expected for the provided pdc constraint under eval. This is due to the use of -start. Solution: Replacing this -start with -setup or by just removing it will fix the issue. ...
2631 - ECP3/FIFO_DC: What's the usage of Bus Ordering Style when using FIFO_DC of Lattice IPExpress which has different data width between write and read port?
FIFO_DC is a flexible IP which allows user to translate bus size from write side to read side. Some examples are given to explain how to select Bus Ordering Style. In the case when write data width is 36 bits and read width is 18 bits. 1. Big Endian ...

Basic & Foundational IPs | FIFO_DC | Knowledge Base

FIFO_DC

235 - All FPGA: How does the output register and read enable (RDEN) signal affect Dual Clock FIFO&nbsp;(FIFO_DC)?

6418 - FIFO for Nexus FPGAs: How does the three FIFO_DC Controller Implementation differs from each other?

7146 - FIFO_DC IP: Does the LSCC_FIFO_DC have First Word Fall Through(FWFT) feature?

2095 - LatticeECP3: How does the Big/Little Endian switch mode affects the functionality of the FIFO DC?

6691 - FIFO_DC IP (Radiant 2023.2 and earlier): How to resolve hold timing violation using the recommended FIFO_DC post-synthesis constraint?

2631 - ECP3/FIFO_DC: What's the usage of Bus Ordering Style when using FIFO_DC of Lattice IPExpress which has different data width between write and read port?

235 - All FPGA: How does the output register and read enable (RDEN) signal affect Dual Clock FIFO (FIFO_DC)?