Issue: Customer only reads ALL-0 input when simultaneously reading and writing on the same address. Root Cause: Wrong EBR primitive is inferred during synthesis. Instead of PDPSC32K, FIFO32K should be used. Details/Notes: The customer intended to ...
The user cannot read and write at the same address at the same time. The IP needs a number of clock cycles before the input data can be available to the output. Please check page 78 of DS102. Please also select "Post-Route Gate-level+Timing" in the ...
The reset signals for the Embedded Block RAM (EBR) based RAM_DQ, RAM_DP, and RAM-DP_TRUE reset only the output registers, not the EBR memory contents. So, if you do not want to reset the output registers of these modules in your design, you can ...
Solution:To modify the Embedded Block RAM (EBR) data through command line, use medit command. User can follow below steps- 1. Load the test project and check the path by using the "pwd" command in Tcl Console. By default, it navigates to the /test ...
Description: This article describes possibility of EBR write clock to be asynchronous to the read clock in iCE40 product. Solution: Yes, the EBR write and read clock could be asynchronous if they are coming from different clock source with different ...
Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...
Lattice Technical Support Expectation Please be advised that highest priority for Lattice Technical Support will be given to 1. Software which is not working as expected or suspected bugs. We recommend that customers use the latest software tools and ...
Title: PCIe DMA in Ring Buffer Operation Mode Cannot Be Stopped Unexpectedly Issue Description: When the PCIe DMA is configured to operate in Ring Buffer DMA mode for continuous transfers, the DMA operation cannot be stopped unexpectedly. If a device ...
Glitch Fliter is used to prevent short-duration events of glitches, This is used to prevent False tripping on noise in a system. GLITCHFilter in device constraints , enables 1ns glitch filtering.
Description: In simulating designs for Lattice devices under Lattice Radiant, this error may appear if there is no GSR instantiated in the testbench. Solution: There is no planned fix for this simulation issue. To work around this, please instantiate ...