RAM_DP
7770 - Avant-AT-G: The instantiated PDPSC32K thru inferring RAM reads ALL-0 input when simultaneously reading and writing on the same address.
Issue: Customer only reads ALL-0 input when simultaneously reading and writing on the same address. Root Cause: Wrong EBR primitive is inferred during synthesis. Instead of PDPSC32K, FIFO32K should be used. Details/Notes: The customer intended to ...
5624 - LatticeECP3: Is it allowed to read and write on the same address at the same time?
The user cannot read and write at the same address at the same time. The IP needs a number of clock cycles before the input data can be available to the output. Please check page 78 of DS102. Please also select "Post-Route Gate-level+Timing" in the ...
3626 - LatticeECP2/M/ECP3/ECP5/ECP5-5G: Can we disable the Reset Signal for RAM_DQ, RAM_DP and RAM_DP_TRUE in our design?
The reset signals for the Embedded Block RAM (EBR) based RAM_DQ, RAM_DP, and RAM-DP_TRUE reset only the output registers, not the EBR memory contents. So, if you do not want to reset the output registers of these modules in your design, you can ...
3538 - Diamond / EBR: Is there an easy way to modify some Embedded Block RAM (EBR) data before running bitgen with encryption enabled?
Solution:To modify the Embedded Block RAM (EBR) data through command line, use medit command. User can follow below steps- 1. Load the test project and check the path by using the "pwd" command in Tcl Console. By default, it navigates to the /test ...
6901 - iCE40: Can the EBR write clock be asynchronous to the read clock?
Description: This article describes possibility of EBR write clock to be asynchronous to the read clock in iCE40 product. Solution: Yes, the EBR write and read clock could be asynchronous if they are coming from different clock source with different ...