3626 - LatticeECP2/M/ECP3/ECP5/ECP5-5G: Can we disable the Reset Signal for RAM_DQ, RAM_DP and RAM_DP_TRUE in our design?

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  If the design requires memory initialization, "pmi_family" parameter should be set to "common". This parameter setting would allow Radiant to build the EBR. For more details, you can refer to Memory Modules User Guide, Chapter 5 (Initializing Memory) ...

• 7738 - Can Global Set/Reset resources be analyzed in Radiant STA tools with Avant?

  Global Set/Reset resources cannot be analyzed in STA tools for both Nexus and Avant devices. For the resource's useability, Users may refer to Global Set/Reset Usage for Nexus Platform Application note found in ...

• 3024 - <span id="lf104285">What are the various ways to produce RAM/ROM in a design? What is the power up state or content of an inferred RAM?</span>

  There are two ways to produce RAM and ROM in a design. You can write code for the design so that the synthesis tool infers the memory or you can instantiate predefined IPexpress or PMI (Parametrized Module Instantiation) memory modules.Inferring ...

• 3767 - What is the limit of writing or reading of Single Port RAM for MachXO2 devices? Why&nbsp;can't I&nbsp;find&nbsp;the exact&nbsp;limit on how&nbsp;fast&nbsp;write or read from&nbsp;Single Port RAM can be done?

  The maximum frequency limit value for Single Port RAM depends on the speed grade and the type of the device (that is ZE/HC/HE). For example, in case of the MachXO2 Breakout Board (MachXO2-7000HE and speed grade 4), the maximum frequency limit of a ...

• 7454 - All Nexus: Why do RTL and gate-level simulations of RAM exhibit mismatched responses during read/write operations?

  Description: The design could have a read/write conflict as both operation may happen simultaneously. Solution: To fix this issue there is an option on the Synthesis Strategy settings which insert additional glue logic to the RAM read/write port to ...