With regards to D-PHY to CMOS v1.3 GUI, if the user happens to encounter the dialogue prompt saying that "the desired frequencies for this configuration could not be generated by the PLL", it means that it is not a recommended value that will be used ...
Please refer to the FPGA-IPUG-02028 document, otherwise known as 1:2 MIPI DSI Display Interface Bandwidth Reducer IP. Table 3.1 shows that the number of lanes is fixed to 4 and non-configurable.
The IP (Intellectual Property) reset signals of the Lattice IP cores are not connected to the GSR components by default. Hence, the users can connect their end design reset signals to the GSR component.