5777 - [CrossLink] [MIPI D-PHY to CMOS Interface Bridge IP]: What can be the cause of frequency calculation error in DPHY to CMOS GPLL after clicking the 'Calculate PLL Frequencies' button of the DPHY-to-CMOS v1.3 Clarity GUI with provided configuration

With regards to D-PHY to CMOS v1.3 GUI, if the user happens to encounter the dialogue prompt saying that "the desired frequencies for this configuration could not be generated by the PLL", it means that it is not a recommended value that will be used for pixel clock.

Thus, the GUI is suggesting to look for another value that will satisfy the PLL frequency.

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5923 - MIPI D-PHY to CMOS Interface Bridge Soft IP: Can the DSI to CMOS IP be changed to DPHY1 from DPHY0?
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5777 - [CrossLink] [MIPI D-PHY to CMOS Interface Bridge IP]: What can be the cause of frequency calculation error in DPHY to CMOS GPLL after clicking the 'Calculate PLL Frequencies' button of the DPHY-to-CMOS v1.3 Clarity GUI with provided configuration

5777 - [CrossLink] [MIPI D-PHY to CMOS Interface Bridge IP]: What can be the cause of frequency calculation error in DPHY to CMOS GPLL after clicking the 'Calculate PLL Frequencies' button of the DPHY-to-CMOS v1.3 Clarity GUI with provided configuration

Related Articles

5923 - MIPI D-PHY to CMOS Interface Bridge Soft IP: Can the DSI to CMOS IP be changed to DPHY1 from DPHY0?

5919 - MIPI D-PHY to CMOS Interface Bridge Soft IP: Why do I get this error message like this: "ERROR - IO register/latch csi2_to_cmos_inst/inst1_inst/lv_ff cannot be implemented in PIC."?

5924 - D-PHY to CMOS v1.2/CrossLink: Why does the DPHY RX channel signal did not move from LP to HS mode?

6946 - What is the spec of 'sync_clk_i' of MIPI D-PHY Rx IP? Does the signal require to be in synced with any other clocks?

7265 - MIPI CSI-2 / DSI D-PHY Transmitter: What is 'Counter Width' parameter in rx_dphy IP and how to calculate the value?