Description: The issue may be due to misaligned data. It should be noted that EPCS-bypassed mode does not have any word alignment capability. However, there is a workaround by using epcs_skipbit_i input signal to correct the data alignment at the ...
There is a PMA register responsible for data polarity inversion that could be written through the APB interface on 10G PCS IP. From Table A.26 of FPGA-TN-02245, look for rx_polinv and tx_polinv where in writing 1 on this register bit will trigger the ...
The Clock Tolerance Compensation (CTC) logic in the SGMII and Gb Ethernet PCS IP Core performs both idle ordered set insertion when the CTC FIFO low watemark is reached and idle ordered set deletion when the CTC FIFO high watemark is reached. CTC ...
Lattice Technical Support Expectation Please be advised that highest priority for Lattice Technical Support will be given to 1. Software which is not working as expected or suspected bugs. We recommend that customers use the latest software tools and ...
Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...
Glitch Fliter is used to prevent short-duration events of glitches, This is used to prevent False tripping on noise in a system. GLITCHFilter in device constraints , enables 1ns glitch filtering.
Description: Nexus device family has a default I2C slave address of 0x40 and you are allow to modify it based on your requirement. Solution: To permanently modify the I2C address, you can modify the desired value in .fea file and use the Programmer ...
Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo.