1138 - Mico32: How to compile and link the Mico32 executable code to be either position-independent or relocatable?

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• 1273 - How can I generate an Intel Hex, or an SREC file from the LatticeMico32 ELF file?

  The LatticeMico32 C/C++ Software Project Environment (SPE) menu allows the compiled C/C++ code to be deployed to on-chip Embedded Block RAM (EBR), or to parallel Flash memory. There is a command line tool that is run in the background that extracts ...

• 7216 - What is the difference, in terms of circuitry and RTL, between the selected mode (Cycle/Time) for choosing the Timeout value of the Watchdog Timer IP?

  The Cycle and Time mode uses the same circuit or RTL. The mode is just to give flexibility to the user to input the Timeout value (either through cycles or periods) through the IP GUI.

• 7179 - GPIO IP Core: How to implement Propel GPIO tristate buffer in RTL?

  User may refer to below RTL code for GPIO bi-directional tri-state buffer assignment. assign gpio = gpio_en_o ? gpio_o : 1'bz; assign gpio_i = gpio;

• 7164 - RISC-V MC/RX/SM IPs: Does the RISC-V CPU reset (i.e. system_resetn_o) signal asynchronous or synchronous?

  Solution: If the debug is enabled, it is synchronous. If not, then it is controlled by an input reset (either synchronous or asynchronous) and by watchdog timer (synchronous). This is valid for the RISC-V RX. Unfortunately RISC-V MC and SM does not ...

• 7501 - RISC-V CPU IP Core: How to achieve cache coherency with RISC-V CPU

  RISC-V cacheable address is configurable in MC, and fixed in RX. The RISC-V core is implementing write through policy, both the cache and destination value will be updated when store operation happen. This imply that CPU store operation will write to ...