7164 - RISC-V MC/RX/SM IPs: Does the RISC-V CPU reset (i.e. system_resetn_o) signal asynchronous or synchronous?

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• 7755 - RISC-V IP: Does the RISC-V Processor Support Vectored Mode Interrupts?

  Description Only RISC-V RX balanced mode and advanced mode support vectored interrupt table. Other RISC-V variant does not support vector interrupt mode. Resolution For RX core, user may find the macro in riscv.h Change it to MTVEC_MODE_VECTORED and ...

• 7754 - RISC-V MC v2.7: Cache Enabled Causing Intermittent Read Corruption

  Description In Propel 2024.2, when RISC-V MC IP Core v2.7 is enabled with cache, user may observe intermittent read corruption when read from non-cacheable memory range. For example: RISC-V MC CPU with cache enabled copy from External Flash to System ...

• 7501 - RISC-V CPU IP Core: How to achieve cache coherency with RISC-V CPU

  RISC-V cacheable address is configurable in MC, and fixed in RX. The RISC-V core is implementing write through policy, both the cache and destination value will be updated when store operation happen. This imply that CPU store operation will write to ...

• 7379 - RISC-V MC CPU IP Core: Does RISC-V AHBL bus support burst transaction?

  Configuration of the RISC-V MC CPU caches is static based. Lattice currently do not support dynamic configuration of caches Lattice cache related API is limited to flushing instruction cache and invalidating data cache. The RISC-V MC perform burst ...

• 7283 - System Memory IP: Does using the Output Register on System Memory IP (AHBL/AXI interface) ensure functionality for the RISC-V MC processor?

  Description: Setup violations in path between RAM and CPU over new extended memory CPU system. Path Begin : ...