How to enable DDR3 SDRAM Controller IP for Certus-NX Devices Golden System Reference Design

Description

The article provides detailed instructions and configurations for integrating DDR3 SDRAM Controller IP into a Certus-NX Versa Evaluation Board system design. It covers clock constraints, FPGA IO location settings, IP configurations, system memory and interconnect updates, address mapping, constraint file modifications, and software project adjustments to enable DDR3 SDRAM usage.

To expand memory usage, a DDR3 SDRAM Controller IP can be instantiated in the reference design to utilize the DDR3 SDRAM on Certus-NX Versa Evaluation Board. The following diagrams show DDR3 SDRAM Controller IP included in the system architecture, clocking scheme, and reset scheme.

Figure 1. GHRD System Architecture with DDR3 SDRAM Controller IP

Note: The AXI4 synchronizer between the AHBL to AXI4 Bridge and DDR3 SDRAM Controller IP is omitted for clarity of the diagram.

Figure 2. GHRD Clocking Overview with DDR3 SDRAM Controller IP

Figure 3. GHRD Reset Overview with DDR3 SDRAM Controller IP

Three components, namely DDR3 SDRAM Controller IP, AXI4 Sync and AHB-Lite to AXI4 Bridge are added to the SoC design. Follow the instructions in section 8.1 Adding Component of the GSRD of Golden System Reference Design and Demo User Guide v1.0 for Certus-NX Devices to add these components. In addition to these instructions, the changes required in the SoC design and software stack are described in this FAQ.

IP Configurations

1. DDR3 SDRAM Controller IP

The DDR3 SDRAM Controller IP enables access to the external DDR3 memory devices. The memory can be used to store CPU software code and data as well as Ethernet packet data.

For more information about the IP core including register map information, refer to DDR3 SDRAM Controller IP Core for Nexus Devices (FPGA-IPUG-02086).

Figure 4. DDR3 SDRAM Controller IP Configuration – General

Figure 5. DDR3 SDRAM Controller IP Configuration – General

2. AXI4 Sync

The AXI4 Sync is clock synchronizer IP which is used to synchronize the clocks between 2 different domains.

Figure 6. AXI4 Sync IP Configuration – General

3. AHB-Lite to AXI4 Bridge

The AHB-Lite to AXI4 Bridge IP is used to convert the AHB-Lite bus transaction at the AHB-Lite Interconnect into AXI4 bus transaction at the DDR3 SDRAM Controller.

For more information about the IP core, refer to AHB-Lite to AXI4 Bridge IP User Guide (FPGA-IPUG-02242).

Figure 7. AHB-Lite to AXI4 Bridge IP Configuration – General

System Memory, AHB-Lite Interconnect and APB Interconnect in the SoC design need to be updated due to the instantiation of DDR3 SDRAM Controller IP.

4. System Memory

Before the addition of DDR3 SDRAM Controller IP, the RISC-V CPU executes instructions from the System Memory with direct connection to INSTR port of RISC-V CPU. After the addition of DDR3 SDRAM Controller, RISC-V CPU can execute instructions from DDR3 SDRAM as well. Hence, the System Memory doesn’t require 2 ports. The updated configuration is shown in the following diagrams.

Figure 8. System Memory IP Configuration – General

Figure 9. System Memory IP Configuration – Port S0 Settings

For more information about the IP , refer to System Memory IP User Guide (FPGA-IPUG-02073).

5. AHB-Lite Interconnect

Changes are required in AHB-Lite Interconnect to accommodate the addition of DDR3 SDRAM Controller and allow access to DDR3 SDRAM by RISC-V CPU.

Figure 10. AHB-Lite Interconnect IP Configuration – General

Figure 11. AHB-Lite Interconnect IP Configuration – Max Burst Size Settings

For more information about the IP core, refer to AHB-Lite Interconnect IP User Guide (FPGA-IPUG-02051).

6. APB Interconnect

The Advanced Peripheral Bus (APB) Interconnect IP is used in system for connecting low-bandwidth, low-power peripherals to the main system bus.  To configure DDR3 SDRAM Controller through APB interface, additional port at the APB Interconnect is required.

For more information about the IP core, refer to APB Interconnect IP User Guide (FPGA-IPUG-02054).

Figure 12. APB Interconnect IP Configuration – General

Address Map

The SoC address map needs to be updated to include DDR3 SDRAM Controller.

Table 1. GHRD Address Map with DDR3 SDRAM Controller

Base Address	End Address	Size	Subordinate
0x0000_0000	0x07FF_FFFF	128 MB	DDR3 SDRAM Controller
0x8000_0000	0x8000_FFFF	64 kB	System Memory
0xC000_0000	0xC000_0FFF	4 kB	UART APB
0xC000_1000	0xC000_1FFF	4 kB	GPIO APB
0xC000_2000	0xC0002_FFF	4 kB	Multi-Boot Config APB
0xC000_3000	0xC000_3FFF	4 kB	SGDMA Controller APB
0xC000_4000	0xC000_7FFF	16 kB	TSE MAC APB
0xC000_8000	0xC000_8FFF	4 kB	Watchdog Timer APB
0xC000_B000	0xC000_BFFF	4 kB	DDR3 APB
0xC000_D000	0xC3FF_FFFF	—	Reserved
0xC400_0000	0xC400_0FFF	4 kB	Octal SPI Controller
0xC400_1000	0xF1FF_FFFF	—	Reserved
CPU Local Memory
0xFFFF_0000	0xFFFF_07FF	2 kB	Timer

Constraint Files

Additional constraints to accommodate DDR3 SDRAM Controller must be added to the existing constraints.sdc and <project_name>.pdc files.

create_clock -name {ddr3_pll_refclk_i} -period 10 [get_ports {ddr3_pll_refclk_i}] #################################################################### DDR3 MC PLL Output Clock #################################################################### create_generated_clock -name {ddr3_clkop} -source [get_pins system_ddr3_mc_inst/lscc_ddr3_mc_top_inst/u0_isccc_ddr3_mc/EN_PLL.u0_ddr_clks/lscc_pll_inst/gen_*_refclk_mon.u_PLL/REFCK] -divide_by 4 -multiply_by 16 \ [get_pins system_ddr3_mc_inst/lscc_ddr3_mc_top_inst/u0_isccc_ddr3_mc/EN_PLL.u0_ddr_clks/lscc_pll_inst/gen_*_refclk_mon.u_PLL/CLKOP] create_generated_clock -name {ddr3_clkos} -source [get_pins system_ddr3_mc_inst/lscc_ddr3_mc_top_inst/u0_isccc_ddr3_mc/EN_PLL.u0_ddr_clks/lscc_pll_inst/gen_*_refclk_mon.u_PLL/REFCK] -divide_by 1 \ [get_pins system_ddr3_mc_inst/lscc_ddr3_mc_top_inst/u0_isccc_ddr3_mc/EN_PLL.u0_ddr_clks/lscc_pll_inst/gen_*_refclk_mon.u_PLL/CLKOS] # Constrain the clocks generated in the DDR3 SDRAM PHY create_generated_clock -name {ddr3_eclkout_w} -source [get_pins system_ddr3_mc_inst/lscc_ddr3_mc_top_inst/u0_isccc_ddr3_mc/EN_PLL.u0_ddr_clks/lscc_pll_inst/gen_*_refclk_mon.u_PLL/CLKOP] -divide_by 1 \ [get_pins system_ddr3_mc_inst/lscc_ddr3_mc_top_inst/u0_isccc_ddr3_mc/NATIVE_ITF.u0_ddr3_mc_wrapper/U1_ddr3_sdram_phy/phy_wrapper_lscc_ddr_mem/DDR_MEM_16_BIT.u0_lscc_ddr_mem_inst/u1_common_logic/u0_ECLKSYNC/ECLKOUT]                    create_generated_clock -name {ddr3_sclk} -source [get_pins system_ddr3_mc_inst/lscc_ddr3_mc_top_inst/u0_isccc_ddr3_mc/NATIVE_ITF.u0_ddr3_mc_wrapper/U1_ddr3_sdram_phy/phy_wrapper_lscc_ddr_mem/DDR_MEM_16_BIT.u0_lscc_ddr_mem_inst/u1_common_logic/u0_ECLKSYNC/ECLKOUT] -divide_by 4 \ [get_pins system_ddr3_mc_inst/lscc_ddr3_mc_top_inst/u0_isccc_ddr3_mc/NATIVE_ITF.u0_ddr3_mc_wrapper/U1_ddr3_sdram_phy/phy_wrapper_lscc_ddr_mem/DDR_MEM_16_BIT.u0_lscc_ddr_mem_inst/u1_common_logic/u0_ECLKDIV/DIVOUT] ####################################################################

Figure 13. Update constraints.sdc

ldc_set_location -site {T5}  [get_ports {ddr3_addr_o[11]}] ldc_set_location -site {R7}  [get_ports {ddr3_addr_o[12]}] #BA ldc_set_location -site {N8}  [get_ports {ddr3_ba_o[0]}] ldc_set_location -site {R8}  [get_ports {ddr3_ba_o[1]}] ldc_set_location -site {M8}  [get_ports {ddr3_ba_o[2]}] #CKE ldc_set_location -site {P9}  [get_ports {ddr3_cke_o[0]}] #CK ldc_set_location -site {T10} [get_ports {ddr3_clk_c_o[0]}] ldc_set_location -site {T9}  [get_ports {ddr3_clk_t_o[0]}] #CS ldc_set_location -site {M9}  [get_ports {ddr3_cs_n_o[0]}] #ODT ldc_set_location -site {N9}  [get_ports {ddr3_odt_o[0]}] #CAS ldc_set_location -site {M10} [get_ports {ddr3_cas_n_o}] #RAS ldc_set_location -site {R9}  [get_ports {ddr3_ras_n_o}] #RESET ldc_set_location -site {P5}  [get_ports {ddr3_reset_n_o}] #WE ldc_set_location -site {L9}  [get_ports {ddr3_we_n_o}] # DQ ldc_set_location -site {R13}  [get_ports {ddr3_data_io[0]}] ldc_set_location -site {N11}  [get_ports {ddr3_data_io[1]}] ldc_set_location -site {T12}  [get_ports {ddr3_data_io[2]}] ldc_set_location -site {R14}  [get_ports {ddr3_data_io[3]}] ldc_set_location -site {T11}  [get_ports {ddr3_data_io[4]}] ldc_set_location -site {P10}  [get_ports {ddr3_data_io[5]}] ldc_set_location -site {P11}  [get_ports {ddr3_data_io[6]}] ldc_set_location -site {R10}  [get_ports {ddr3_data_io[7]}] ldc_set_location -site {M12}  [get_ports {ddr3_data_io[8]}] ldc_set_location -site {L12}  [get_ports {ddr3_data_io[9]}] ldc_set_location -site {M11}  [get_ports {ddr3_data_io[10]}] ldc_set_location -site {N13}  [get_ports {ddr3_data_io[11]}] ldc_set_location -site {M16}  [get_ports {ddr3_data_io[12]}] ldc_set_location -site {M13}  [get_ports {ddr3_data_io[13]}] ldc_set_location -site {M14}  [get_ports {ddr3_data_io[14]}] ldc_set_location -site {N14}  [get_ports {ddr3_data_io[15]}] # DQS ldc_set_location -site {R12}  [get_ports {ddr3_dqs_io[0]}] ldc_set_location -site {N16}  [get_ports {ddr3_dqs_io[1]}] # DM ldc_set_location -site {N12}  [get_ports {ddr3_dm_o[0]}] ldc_set_location -site {P14}  [get_ports {ddr3_dm_o[1]}]

Figure 14. Update <Project_Name>.pdc

Bootloader and Application Software Projects

To enable DDR3 SDRAM Controller, follow these steps to update both the bootloader and application C/C++ software projects.

1. Create the bootloader and application C/C++ projects by using Propel SDK with the sys_env.xml file generated from Propel Builder SoC project that includes DDR3 SDRAM Controller.

2. Change the bootloader section address to load to DDR3 SDRAM start and end addresses. Also, update the offset of the CRC check for the application software.

Figure 15. Update DDR3 SDRAM start address, end address, and offset for CRC checksum

3. Call the DDR3 SDRAM Controller init function inside the bootloader C/C++ project.

Figure 16. Call DDR3 SDRAM Controller init function inside bootloader

4. Rebuild the bootloader project to generate the mem file.

5. Follow the steps in section 8.3 Using ECO Editor in the GSRD of Golden System Reference Design and Demo User Guide v1.0 for Certus-NX Devices for integration of mem file into bitstream.

6. For the application software project, update the linker file inside C/C++ application software.

Figure 17. Update application software linker start address to 0x0

7. Because this SoC design with DDR3 SDRAM Controller has cache enabled, you will need to add cache invalidation code in the application software when SGDMA RX interrupt is triggered. The function will fetch the updated descriptor and data packets from DDR3 SDRAM to the cache.

Figure 18. Call cache_invalidate_all function to fetch new data to cache

8. Rebuild the C/C++ application software project.

9. Follow the steps in section 6.4 Programming Standalone Golden or Primary GSRD Bitstream and Application Software of the GSRD of Golden System Reference Design and Demo User Guide v1.0 for Certus-NX Devices to program both binary file and bitstream into the SPI flash and run the reference design.

10. Once the system boots up, you should see the following output at UART terminal.

Figure 19. Application software boots up from DDR3 SDRAM

Reference

1. GHRD/GSRD Landing Page: https://www.latticesemi.com/products/designsoftwareandip/intellectualproperty/demos/ghrd-gsrd-demonstration
   
2. Certus-NX Golden System Reference Design and Demo V1.0 - User Guide (FPGA-RD-02323)
   
3. DDR3 SDRAM Controller IP Core for Nexus Devices (FPGA-IPUG-02086)
   
4. AHB-Lite to AXI4 Bridge IP User Guide (FPGA-IPUG-02242)
   
5. System Memory IP User Guide (FPGA-IPUG-02073)
   
6. APB Interconnect IP User Guide (FPGA-IPUG-02054)
   

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