7283 - System Memory IP: Does using the Output Register on System Memory IP (AHBL/AXI interface) ensure functionality for the RISC-V MC processor?
Description:
Setup violations in path between RAM and CPU over new extended memory CPU system.
Path Begin : cpu_system_i/cpu_mem_i/lscc_sys_mem_inst/CORE_MEMORY.genblk1.u_lscc_mem0/intf_AHBL.lifcl_LAVAT.lram.dp.ulram_0/genblk2[0].genblk3.ulram_core0/u_lram0.LRAM_inst/DOA30 (LRAM_CORE_LRAM_CORE_R1C3)
Path End : cpu_system_i/risc_v_cpu_i/riscvsmall_inst/secured_instance_157_5/secured_instance_156_3544/ADR5 (EBR_CORE_EBR_CORE_R19C8)
Source Clock : OSCA_FOR_CRE_INST_inst_hf_clk_out_o (R)
Destination Clock: OSCA_FOR_CRE_INST_inst_hf_clk_out_o (R)
Logic Level : 14
Delay Ratio : 30.6% (route), 69.4% (logic)
Clock Skew : -0.291 ns
Setup Constraint : 22.222 ns
Common Path Skew : 0.210 ns
Path Slack : -0.832 ns (Failed)
Solution:
- There is no problem using the Output Register on the System Memory IP interfaced with the RISC-V MC processor.
- However, increased Fmax from the output register causes processor DMIPS to drop (this is due to the additional clock cycle burst).
- However, if the cache option is considered in RISC-V MC, it minimizes the DMIPS tradeoff. DMIPS tradeoff is not significant since the data is often cached and avoids fetching from the System Memory.