7755 - RISC-V IP: Does the RISC-V Processor Support Vectored Mode Interrupts?

Description

Only RISC-V RX balanced mode and advanced mode support vectored interrupt table.

Other RISC-V variant does not support vector interrupt mode.

Resolution

For RX core, user may find the macro in riscv.h

Change it to MTVEC_MODE_VECTORED and it will enable vectored mode.

The vector table can be found in entry.S. User may modify it to point to different trap(interrupt) handler.

Notice that the vectored interrupt is for different types of interrupts, not the interrupts IRQ numbers.

The following contents are reference from RISC-V privileged spec 20211203.
When MODE=Vectored, all synchronous exceptions into machine mode cause the pc to be set to the address in the BASE field, whereas interrupts cause the pc to be set to the address in the BASE field plus four times the interrupt cause number. For example, a machine-mode timer interrupt (see Table 3.6 on page 39) causes the pc to be set to BASE+0x1c.
And the table is as following:



Enabling vector interrupt may not improve interrupts response time. Other suggestion for this purpose includes:

1. Do not use system memory/external memory to store the trap handlers. Store trap handler inside TCM may yield 10x to 20x improvement in response time than AXI memory.
   
2. Assign the IRQ port of those IPs to small numbers of CPU's IRQ ports, because the driver iterates from small numbers to large numbers.
   

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