1. RISC-V cacheable address is configurable in MC, and fixed in RX.
2. The RISC-V core is implementing write through policy, both the cache and destination value will be updated when store operation happen.
3. This imply that CPU store operation will write to destination, while load operation always read cache if hit.
4. In order to read the latest value from source, invalidate is required before load.
5. In the case when RISC-V is use with SGDMA IP code, SGDMA driver does not has the capability to perform cache related operation. SGDMA will always read directly from source and same for write, thus not affected by RISC-V cacheable address range.
6. If the RISC-V core place the SGDMA buffer descriptor in cacheable memory address, then invalidate is required before reading back for status. Same for destination buffer address.

To achieve data coherency:

Use case 1 - cacheable address (user must perform cache flush when CPU write to cacheable memory address, for other host to retrieve updated data value from that memory address location)

1. RISC-V write to target cacheable memory address, perform cache flush to update the latest value to target memory address - this step may not require cache flush due to Lattice RISC-V write through policy.
2. Soft IP host read updated data from target memory address
3. Soft IP host write to target memory address, Soft IP direct memory map will write into actual memory address 
4. RISC-V read updated data from memory address - RISC-V must invalidate the cache line before reading the updated data

Use case 2 - non-cacheable address (cache flush not required)

1. RISC-V write to target non-cacheable memory address
2. Soft IP read data from target memory address