7754 - RISC-V MC v2.7: Cache Enabled Causing Intermittent Read Corruption
Description
- In Propel 2024.2, when RISC-V MC IP Core v2.7 is enabled with cache, user may observe intermittent read corruption when read from non-cacheable memory range.
- For example: RISC-V MC CPU with cache enabled copy from External Flash to System Memory. User may observe certain memory range was read as "0".
- Depends on end user use cases, it may result in functional failure if CPU is performing remote update to System Memory, which result in memory corruption
- By default RISC-V cache is not enabled. User will only experience this issue intermittently when they continuously read from a non-cacheable memory
- Failing condition and Tool/IP version
- Only when cache is enabled
- Specific to RISC-V MC IP Core v2.7 (v2.6 and below not affected)
- Propel v2024.2 and v2024.2.1
Resolution:
- Disable cache for RISC-V MC v2.7
- Recommended to upgrade to RISC-V v2.8 in Propel 2025.1 if cache enabled is a MUST requirement
- If cache is required for RISC-V MC v2.7, patch per request basis for Propel v2024.2 and v2024.2.1, engage Tech Support for RISC-V MC v2.7 patch request
Related Articles
7755 - RISC-V IP: Does the RISC-V Processor Support Vectored Mode Interrupts?
Description Only RISC-V RX balanced mode and advanced mode support vectored interrupt table. Other RISC-V variant does not support vector interrupt mode. Resolution For RX core, user may find the macro in riscv.h Change it to MTVEC_MODE_VECTORED and ...7379 - RISC-V MC CPU IP Core: Does RISC-V AHBL bus support burst transaction?
Configuration of the RISC-V MC CPU caches is static based. Lattice currently do not support dynamic configuration of caches Lattice cache related API is limited to flushing instruction cache and invalidating data cache. The RISC-V MC perform burst ...7501 - RISC-V CPU IP Core: How to achieve cache coherency with RISC-V CPU
RISC-V cacheable address is configurable in MC, and fixed in RX. The RISC-V core is implementing write through policy, both the cache and destination value will be updated when store operation happen. This imply that CPU store operation will write to ...7164 - RISC-V MC/RX/SM IPs: Does the RISC-V CPU reset (i.e. system_resetn_o) signal asynchronous or synchronous?
Solution: If the debug is enabled, it is synchronous. If not, then it is controlled by an input reset (either synchronous or asynchronous) and by watchdog timer (synchronous). This is valid for the RISC-V RX. Unfortunately RISC-V MC and SM does not ...7283 - System Memory IP: Does using the Output Register on System Memory IP (AHBL/AXI interface) ensure functionality for the RISC-V MC processor?
Description: Setup violations in path between RAM and CPU over new extended memory CPU system. Path Begin : ...