Description: Due to a known issue in Timer/Counter IP Core v1.3.0, user may observed that interrupt is not generated during counter timeout. Solution: To workaround this issue, please revert back to Timer/Counter IP Core v1.2.2. This is scheduled to ...
RISC-V cacheable address is configurable in MC, and fixed in RX. The RISC-V core is implementing write through policy, both the cache and destination value will be updated when store operation happen. This imply that CPU store operation will write to ...
The Feedthrough IP allows you to export the specific AMBA bus out from the Lattice Propel Builder system to the higher-level module. Please refer to FPGA-AN-02072-1.0: Lattice RISC-V Embedded Design Guidelines for more information on the application ...
Description: This is due to a software bug in gp_timer.c where the gp_timer_config and gp_timer_stop API used reg_32b_write instead of read-modify-write reg_32b_modify. When write to control register, it overwrite the register value instead of ...
Description The article provides detailed instructions and configurations for integrating DDR3 SDRAM Controller IP into a Certus-NX Versa Evaluation Board system design. It covers clock constraints, FPGA IO location settings, IP configurations, ...