7449 - Timer/Counter IP Core v1.3.0: Why Timer/Counter does not generate interrupt (IRQ)?

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• 6784 - Propel / Timer/Counter IP version 1.2.0 or earlier: Why is CPU hanging in debug when the number of timers set on the Timer/Counter IP GUI is 1?

  Description: This error will only be observed when performing Open OCD debugging. A hang will be observed while doing a step-through debugging. This is caused a bug on the python script that generates the IP RTL. There is a NUM_OF_TIMERS parameter on ...

• 7501 - RISC-V CPU IP Core: How to achieve cache coherency with RISC-V CPU

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• 7035 - Propel: Why Propel Timer/Counter IP register settings were reset when I start/stop the timer with driver API?

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