Solution Stacks | Demo & Reference Design Source Code

Demo & Reference Design Source Code
Hold Time Violations When Compiling EtherCAT with Single-Axis Motor Control Reference Design in Lattice Radiant 2025.2.1
Description When you compile FPGA-RD-02342: EtherCAT with Single-Axis Motor Control Reference Design in Lattice Radiant 2025.2.1, Place & Route may report persistent hold-time violations even though setup timing closes with comfortable margin. After ...
7525 - How to request the Lattice Sentry 3.0 Solution for Lincoln City?
To obtain the Lattice Sentry 3.0 for Lincoln City project files, please ensure that you have an active Non-Disclosure Agreement (NDA) with Lattice Semiconductor. To submit the NDA request, please go to this link to : http://www.latticesemi.com/nda ...
6057 - CrossLink: Where can we get the excel sheet filename: sublvds2csi2_clock.xlsx described in FPGA-RD-02061 to calculate the pixel and byte clock and others from RX bandwidth and other information which can be helpful to configure IPs?
The file is found in the docs folder of the sublvds2csi2_rd1_0_pkg when you download the source code (link: https://www.latticesemi.com/view_document?document_id=52697) from SubLVDS to MIPI CSI-2 Image Sensor Bridge webpage (link: ...
6133 - CrossLink: Is there any reference design that uses 2 IP core solutions using CSI-2/DSI D-PHY Receiver and Byte to Pixel Converter?
Solution: Currently, we do not have a direct reference design from CSI-2/DSI D-PHY Receiver and byte-to-pixel converter. However, you may refer to MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge (link: ...

Solution Stacks | Demo & Reference Design Source Code | Knowledge Base

Demo & Reference Design Source Code

Hold Time Violations When Compiling EtherCAT with Single-Axis Motor Control Reference Design in Lattice Radiant 2025.2.1

7525 - How to request the Lattice Sentry 3.0 Solution for Lincoln City?

6057 - CrossLink: Where can we get the excel sheet filename: sublvds2csi2_clock.xlsx described in FPGA-RD-02061 to calculate the pixel and byte clock and others from RX bandwidth and other information which can be helpful to configure IPs?

6133 - CrossLink: Is there any reference design that uses 2 IP core solutions using CSI-2/DSI D-PHY Receiver and Byte to Pixel Converter?