6057 - CrossLink: Where can we get the excel sheet filename: sublvds2csi2_clock.xlsx described in FPGA-RD-02061 to calculate the pixel and byte clock and others from RX bandwidth and other information which can be helpful to configure IPs?
6057 - CrossLink: Where can we get the excel sheet filename: sublvds2csi2_clock.xlsx described in FPGA-RD-02061 to calculate the pixel and byte clock and others from RX bandwidth and other information which can be helpful to configure IPs?
Solution: Currently, we do not have a direct reference design from CSI-2/DSI D-PHY Receiver and byte-to-pixel converter. However, you may refer to MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge (link: ...
Description When you compile FPGA-RD-02342: EtherCAT with Single-Axis Motor Control Reference Design in Lattice Radiant 2025.2.1, Place & Route may report persistent hold-time violations even though setup timing closes with comfortable margin. After ...
No. The current reference design, RD1097, supports only the resolutions between 1024x768@60Hz(65MHz pixel frequency) to 1600x1200@60Hz(162MHz pixel frequency). You can get detailed information from Table 6 and Table 7, RD1097.
The DSI-RX Reference Design (RD1185) supports all video transmission modes defined in the MIPI DSI Specification v1.1: - Non-Burst Mode with Sync Pulses - Non-Burst Mode with Sync Events - Burst mode The DSI-TX Reference Design (RD1184) supports two ...