6057 - CrossLink: Where can we get the excel sheet filename: sublvds2csi2_clock.xlsx described in FPGA-RD-02061 to calculate the pixel and byte clock and others from RX bandwidth and other information which can be helpful to configure IPs?

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• 6133 - CrossLink: Is there any reference design that uses 2 IP core solutions using CSI-2/DSI D-PHY Receiver and Byte to Pixel Converter?

  Solution: Currently, we do not have a direct reference design from CSI-2/DSI D-PHY Receiver and byte-to-pixel converter. However, you may refer to MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge (link: ...

• 4144 - For Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) Rx Design i.e RD1185, is there any minimum time period requirement for reset of FPGA ? Does it come out of reset after a valid Data clock (DCK) is available?

  There are no requirements for the reset. It is an asynchronous logic reset.

• 2392 - [LatticeECP3]: Can Lattice's reference design "HDMI/DVI Interface" support all resolutions defined in HDMI/DVI specification?

  No. The current reference design, RD1097, supports only the resolutions between 1024x768@60Hz(65MHz pixel frequency) to 1600x1200@60Hz(162MHz pixel frequency). You can get detailed information from Table 6 and Table 7, RD1097.

• 3802 - MIPI DSI Receive Bridge:  Which video transmission modes are supported by Lattice DSI-RX Reference Design - RD1185?

  The DSI-RX Reference Design (RD1185) supports all video transmission modes defined in the MIPI DSI Specification v1.1: - Non-Burst Mode with Sync Pulses - Non-Burst Mode with Sync Events - Burst mode The DSI-TX Reference Design (RD1184) supports two ...

• 2393 - [LatticeECP3]: Can Lattice's reference design "HDMI/DVI Interface" support audio function?

  With the reference design UG36-- "HDMI/DVI Interface", we provide raw data signals "rx_ade/rx_audio_ch0[3:0]/rx_audio_ch1[3:0]/rx_audio_ch2[3:0]". The user may get audio data by decoding the signals according to HDMI specification. To output audio ...