3802 - MIPI DSI Receive Bridge:  Which video transmission modes are supported by Lattice DSI-RX Reference Design - RD1185?

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• 4144 - For Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) Rx Design i.e RD1185, is there any minimum time period requirement for reset of FPGA ? Does it come out of reset after a valid Data clock (DCK) is available?

  There are no requirements for the reset. It is an asynchronous logic reset.