Description: Due to a known issue in Timer/Counter IP Core v1.3.0, user may observed that interrupt is not generated during counter timeout. Solution: To workaround this issue, please revert back to Timer/Counter IP Core v1.2.2. This is scheduled to ...
Description: This error will only be observed when performing Open OCD debugging. A hang will be observed while doing a step-through debugging. This is caused a bug on the python script that generates the IP RTL. There is a NUM_OF_TIMERS parameter on ...
Description: This is due to a software bug in gp_timer.c where the gp_timer_config and gp_timer_stop API used reg_32b_write instead of read-modify-write reg_32b_modify. When write to control register, it overwrite the register value instead of ...
Lattice Technical Support Expectation Please be advised that highest priority for Lattice Technical Support will be given to 1. Software which is not working as expected or suspected bugs. We recommend that customers use the latest software tools and ...
Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...
Glitch Fliter is used to prevent short-duration events of glitches, This is used to prevent False tripping on noise in a system. GLITCHFilter in device constraints , enables 1ns glitch filtering.
Description: Nexus device family has a default I2C slave address of 0x40 and you are allow to modify it based on your requirement. Solution: To permanently modify the I2C address, you can modify the desired value in .fea file and use the Programmer ...
Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo.