Description: Due to a known issue in Timer/Counter IP Core v1.3.0, user may observed that interrupt is not generated during counter timeout. Solution: To workaround this issue, please revert back to Timer/Counter IP Core v1.2.2. This is scheduled to ...
Description: This error will only be observed when performing Open OCD debugging. A hang will be observed while doing a step-through debugging. This is caused a bug on the python script that generates the IP RTL. There is a NUM_OF_TIMERS parameter on ...
Description: This is due to a software bug in gp_timer.c where the gp_timer_config and gp_timer_stop API used reg_32b_write instead of read-modify-write reg_32b_modify. When write to control register, it overwrite the register value instead of ...
Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...
Lattice Technical Support Expectation Please be advised that highest priority for Lattice Technical Support will be given to 1. Software which is not working as expected or suspected bugs. We recommend that customers use the latest software tools and ...
Glitch Fliter is used to prevent short-duration events of glitches, This is used to prevent False tripping on noise in a system. GLITCHFilter in device constraints , enables 1ns glitch filtering.
Description: In simulating designs for Lattice devices, this error may appear if there is no GSR instantiated in the testbench. Solution: There is no planned fix for this simulation issue. To work around this, please instantiate GSR on your ...
Solution: The following RDs available for Crosslink-NX will support the said applications: 1. FPGA-RD-02212 : N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation - Aggregate multiple Image Sensors into a single Output with Minimal Latency. - Uses ...