Description: Due to a known issue in Timer/Counter IP Core v1.3.0, user may observed that interrupt is not generated during counter timeout. Solution: To workaround this issue, please revert back to Timer/Counter IP Core v1.2.2. This is scheduled to ...
Description: This error will only be observed when performing Open OCD debugging. A hang will be observed while doing a step-through debugging. This is caused a bug on the python script that generates the IP RTL. There is a NUM_OF_TIMERS parameter on ...
Description: This is due to a software bug in gp_timer.c where the gp_timer_config and gp_timer_stop API used reg_32b_write instead of read-modify-write reg_32b_modify. When write to control register, it overwrite the register value instead of ...