5239 - [ECP5/ECP5-5G]: How to fix "timeout error" when debugging the soft-core after programming the bitstream in the FPGA?
Divide TCK signal of JTAG by 10 on Lattice parameter.
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Why FPGA Programming Failure When JTAG Chain Has 7 or More Devices?
DESCRIPTION When programming Lattice FPGA devices via SPI Flash using a JTAG chain, the Erase-Program-Verify (EPV) operation fails deterministically starting from the 7th device in the chain. Chains of 6 devices or fewer complete SPI Flash EPV ...
2125 - What is the device programming time of a Lattice FPGA?
Solution: The time to program a Lattice FPGA is dependent on several factors including configuration mode, programming speed, and device size. Some configuration modes and methods are faster than others. The complete configuration time inherently ...
6186 - Lattice Radiant Programmer: How user can Flash FPGA binary file (.rbt) and Propel SDK (RISC-V) binary file to Lattice FPGA?
To flash FPGA binary file (.rbt) user can use the provided C source code in the Lattice software installation directory for embedded programming. C source code for Radiant: <install_path>\programmer\embedded_source Example: C:\lscc\radiant\<Radiant ...
7757 - Radiant Programmer: What is Erase, Program, Verify Quad 1 operation used for?
Description: Erase, Program, Verify Quad 1 enables that QE bit to '1'. In general, there are two (2) requirements/steps to enable booting from external SPI Flash through x4 (QUAD Mode) Step 1 - Convert the bitstream file into hex (Quad I/O read mode) ...
6179 - How do user program Lattice FPGA after programming a bitstream to the SPI Flash with JTAG_PORT and MASTER_SPI_PORT set to DISABLED?
Description: When JTAG_PORT and MASTER_SPI_PORT is set to DISABLED, user can no longer access the configuration logic through JTAG and MSPI Port. Thus, user can't perform programming with the interface. Solution: To workaround on this, user can ...