2695 - LatticeECP3: Can LatticeECP3's 2.5Gbps Ethernet PCS IP and 2.5Gbps Ethernet MAC IP run together at 1 GbE rates?
The LatticeECP3 2.5 GBE MAC and PCS IPs described in IPUG98 and IPUG99, will run at 1.25 Gbps by changing the ref_clk clock source to 125 Mhz as shown in the "PHY with Host Bus Control Interface" figure of IPUG99. The byte_clk and word_clk will be 125 MHZ and 62.5 MHZ respectively, as one would expect. Also, the hardware validation shown in Chapter 6 of IPUG99 was actually tested at 1.25 Gbps.
As you switch between 3.125 Gbps (2.5 GbE) and 1.25 Gbps (1 GbE) rates, you also need to change the the LatticeECP3 PCS PLL/CDR register DIVIDER settings accordingly. There are two ways to achieve this:
- You can generate 2 separate bitstreams: one bitstream with the PCS/SERDES configured in IPexpress for 1.25 Gbps/125 Mhz refclk and another one with the PCS/SERDES configured for 3.125 Gbps/312.5 Mhz refclk
- You can use the PCS/SERDES SCI interface directly in your design to access the LatticeECP3 PCS/SERDES registers to change the PLL/CDR register DIVIDER settings in real time depending on whether you run 1.25 or 3.125 Gbps:
- The TX_DATARATE_RANGE and RX_DATARATE_RANGE attributes are used to tweak the PLL and CDR VCO divider settings (see the "SERDES_PCS GUI Attributes - Reference Clocks Setup Tab" table of TN1176). The settings are different between 1.25 Gbps ("MED") and 3.125 Gbps ("HIGH").
- The "Attribute Cross-Reference" Table of TN1176 shows the relationship between these attributes and the register bit settings for the PLL/CDR VCO Dividers:
- for 1.25 Gbps (MED), you should set QD_0D[2:0] to "010" and CH_10[2:0] to "010"
- For 3.125 Gbps (HIGH), you should set QD_0D[2:0] to "000" and CH_10[2:0] to "000"
Note that Lattice Semiconductor does not recommend or support using the SCI interface to make changes to the LatticeECP3 PCS/SERDES registers beyond the scope of this FAQ.