1578 - For a DDR2 memory controller countinous read, is a new read pulse required per Burst (4 clock cycles) or only when the read sequence has been interrupted by other commands?

You do not need to issue a new read pulse for continuous read since there is no postamble between the reads. If there is a postamble between read bursts, then a new read pulse is required.

Related Articles
7747 - Avant: DDR Memory Controller Revision and Migration Guide
Description: This table is to provide guidelines to help customers select the appropriate Memory Controller IP for Avant devices in accordance to the supported Memory Controller IP version in Radiant Software Tools. User may choose to continue to use ...
7759 - DDR Memory Controller v2.6.0 - Driver API caused invalid training status
Description: The driver API for DDR Memory Controller v2.6.0, DDR_MC_DONE_BITS in ddr_mc_avant.h is incorrect and causing invalid training status. Wrong value: #define DDR_MC_DONE_BITS 0x0000007D Correct value: #define DDR_MC_DONE_BITS 0x0000007F ...
6979 - PCIe for Nexus FPGAs: Does the vc_tx_valid_i can be delayed (insert 3 clock cycles) during long external memory read since the FPGA lose the access for some clocks?
Description: The vc_tx_valid_i should not be delayed or do insertion of the 3 clock cycles gap within packets as it affects the validity of the data thus it is forbidden to insert such delay. This cannot be use as a workaround for the long external ...
1710 - LatticeECP3: How do I implement multiple DDR2/3 memory interfaces in one side of LatticeECP3 when there is only one DQSDLL available per side?
LatticeECP3 devices have one DQSDLL per side. DQSDLL has an input port called UDDCNTLN that allows its DLL code value (DQSDEL output) to be updated while it is asserted Low. The updated code value is used to generate precise PVT (Process Voltage ...
2319 - [LatticeECP3]: Should I reset the Lattice DDR3 controller IP core after changing the "read_pulse_tap" signal?
The "read_pulse_tap" port is an input signal to the DDR3 controller IP core. Each DQS group has its own 3-bit read_pulse_tap port to control the READ signal timing to the DQSBUF hardware module. The DDR3 IP core allows dynamic READ pulse timing ...

1578 - For a DDR2 memory controller countinous read, is a new read pulse required per Burst (4 clock cycles) or only when the read sequence has been interrupted by other commands?

1578 - For a DDR2 memory controller countinous read, is a new read pulse required per Burst (4 clock cycles) or only when the read sequence has been interrupted by other commands?

Related Articles

7747 - Avant: DDR Memory Controller Revision and Migration Guide

7759 - DDR Memory Controller v2.6.0 - Driver API caused invalid training status

6979 - PCIe for Nexus FPGAs: Does the vc_tx_valid_i can be delayed (insert 3 clock cycles) during long external memory read since the FPGA lose the access for some clocks?

1710 - LatticeECP3: How do I implement multiple DDR2/3 memory interfaces in one side of LatticeECP3 when there is only&nbsp;one DQSDLL&nbsp;available per side?

2319 - [LatticeECP3]: Should I&nbsp;reset the Lattice DDR3 controller IP core after changing the&nbsp;"read_pulse_tap" signal?

1710 - LatticeECP3: How do I implement multiple DDR2/3 memory interfaces in one side of LatticeECP3 when there is only one DQSDLL available per side?

2319 - [LatticeECP3]: Should I reset the Lattice DDR3 controller IP core after changing the "read_pulse_tap" signal?