Solution: To slow down the edge rate (that is reduce drive strength), set the drive strengths from the default 8 mA to lower drive strengths using the Lattice Diamond ECO editor. The ECO editor tool can be used to change the sysCONFIG pin settings. ...
The eco_config_memory command only works when used via Radiant GUI flow since the ECO editor is readily available in the software. When using non-GUI project flow (TCL), the ECO editor must be called using "ecoc" command and the ECO commands should ...
Description: In Lattice Diamond ECO Editor prompted DRC Error after assigning IO pin on the signal probe and unable to assign other IO_type. Error - ChipCheck: comp CLOCK_i and $COMP_33 have incompatible VCC requirements. Solution: To workaround this ...
Description: This is a known issue in Radiant v2022.1 and v2023.1. The ECO editor for memory initialization is not reflected in updated bitstream. Solution: To workaround this issue, you may revert back to Radiant v3.2 or request a software patch for ...
Lattice Technical Support Expectation Please be advised that highest priority for Lattice Technical Support will be given to 1. Software which is not working as expected or suspected bugs. We recommend that customers use the latest software tools and ...
Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...
Glitch Fliter is used to prevent short-duration events of glitches, This is used to prevent False tripping on noise in a system. GLITCHFilter in device constraints , enables 1ns glitch filtering.
Description: Nexus device family has a default I2C slave address of 0x40 and you are allow to modify it based on your requirement. Solution: To permanently modify the I2C address, you can modify the desired value in .fea file and use the Programmer ...
Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo.