7758 - Propel Builder v2025.1: DRC update for AXI base address require to be multiple of its address range
Description:
A new DRC is implemented
for AXI base address in Propel 2025.1 where base address of a component should be a multiple of its address range.
The DRC related to AXI base
address assignment was not present in Propel versions 2024.1 and 2024.2. The Builder engine is enhanced in 2025.1 to validate base addresses based on the IP configuration and the updated DRC will notify
and block users when invalid base address configurations are detected. This
change improves robustness but may require rework in existing projects.
What is the DRC update?
Base address of a component
(in this case LPDDR4 Memory Controller) should be a multiple of its address
range.
- Example: LPDDR4 Memory Controller
have 1GB range (which is 0x40000000 in hex), then valid aligned base address
would be: 0x00000000, 0x40000000, 0x80000000, 0xC0000000,
etc.
Why is this required?
Two key issues may occur
in older versions of Propel (2024.2 and earlier) if this DRC rule is not followed:
- No address translation in
the interconnect
- The Lattice interconnect does not subtract the base address when forwarding the
AXI address to the subordinate. It just checks if the address is within the
[Base, Base + Range) window and forwards it as-is.
- If user LPDDR4 controller
expects addresses starting from 0x00000000, but was assigned as 0xA0000000, it will
receive that full address — and since it only uses the lower 30 bits, it will
interpret it incorrectly.
- Subordinate modules assume
alignment
- Some IPs (like the LPDDR4 controller) are designed assuming the base address is
aligned. For example, if it only uses the lower 30 bits of the address, then:
- 0x80000000 becomes 0x00000000
(OK)
- 0xA0000000 becomes 0x20000000 (NOT OK — this shifts the entire memory map)
- This causes a mismatch between what the AXI master thinks it's accessing and
what the memory controller actually sees.