The Control Register is used to control the device during and after a configuration.
[31:30] Core CLK SEL
Control bits to set the core clock frequency respect the internal oscillator frequency.
00 Fosc/2
01 Fosc/4
10 Fosc/5
11 Fosc/6
29 WKUP TRAN
Control bit transparent reconfiguration. When this bit is set to “0”, the wake-up signals GOE and GSRN
will go low during reconfiguration. When this bit is set to “1”, the wake-up signals GOE and GSRN will stay
high during reconfiguration
28 TransFR (previously known as NDR)
Control bit for supporting Leave Alone IO for reconfiguration. Please refer to the Non-Disruptive
Reconfiguration Specification (http://speedy:8000/isp/documents/ndr(106193).doc) for a more detailed
description.
27 No BKE
Control bit to bypass auto SRAM Bulk Erase for partial re-configuration
26 No CDM
Control bit to bypass CDM downloading for refresh or programb_pin toggle.
25 TranEdit
Control bit to enable the write operation to the SRAM array in transparent mode
24 HFC HD
Control bit to enable the hardening when device wake up.
23 SSPI Auto
Slave SPI Configuration Mode to read a bitstream instead of performing manual operation.
22 CPU Manual
Control bit to set CPU mode to perform manual operation instead of reading a bitstream.
21 SRME
This control bit is the Slow Response Mode Enable bit, which enable the automatic insertion of the Lattice
specific protocol to handle the issue caused by the slow response of the flash or SRAM operation for high
speed configuration slave mode read. If this bit is set, the bit[11:10] options (STX_DUM) is discarded, and
a non-deterministic number of all “1” bytes followed by one “0” byte will be added before the first readback
data frame for incremental read commands.
20 SPIM
Control bit for Master SPI boot address selection. If set to “1”, use boot address from SRAM bits or CIB
(depend on mc1_source_sel). If set to “0”, use hard coded boot address (H000000 for single boot;
H010000 for dual boot primary; HFFFF00 for dual boot secondary)
[19:18] P_DONE Control
PROGRAM_DONE overload control option for bitstream. If bit 19 is set to “1”, the PROGRAM_DONE
command is set to overload with either the BYPASS or FLOW_THROUGH function, depending on bit 18.
10 Overload with BYPASS
11 Overload with FLOW_THROUGH
0X No Overload (Default)
[17:15] INITN OPT
INITN pin optional control. Bit 17 determines if the INITN pin is controlled by the configuration circuitry or
the bit 15 of the control register 0. If bit 17 is set to “1”, bit 15 will override the configuration circuitry.
[14:12] DONE OPT
DONE pin optional control. Bit 14 determines if the DONE pin behavior as governed by the configuration
circuitry can be overridden by bit 12 of control register 0. If bit 14 is set to “1”, the DONE pin is overridden
by the bit 12. Bit 13, if set to 0 connects Done pin to internal pull-up while 1 Connect to Active Drive.
[11:10] STX DUM
These two control bits determine the number of dummy bytes padding to add before the first frame is read
out during incremental bitstream readback (slave mode). 00 means 0 # of Dummy Bytes Padding to insert, 01 means 4, 10 means 8 , 11 means 16
9 MCLK Bypass
This control bit to enable the bypass clock output in master bypass mode
8 LSBF
Control bit for Master MSPI to send out commands and address least significant bit first.
7 CPOL
This control bit select an inverted or non-inverted clock
è 0 = Active high clocks selected. In idle state clock is low
è 1 = Active low clocks selected. In idle state clock is high
6 CPHA
This Control bit is used to select the clock format.
è 0 = sampling of data occurs at the rising edge of the clock
è 1 = sampling of data occurs at the falling edge of the clock
[5:0] Master Clock Divider: Control bit that divides the clock coming from the on-chip oscillator. The definition of the divider values is
defined in the oscillator T-Spec for each individual device family