285 - Lattice Diamond: Can I replace the dummy bits in the LatticeECP3 bitstream header with custom data (revision ID for example)?

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  The Control Register is used to control the device during and after a configuration. [31:30] Core CLK SEL Control bits to set the core clock frequency respect the internal oscillator frequency. 00 Fosc/2 01 Fosc/4 10 Fosc/5 11 Fosc/6 29 WKUP TRAN ...

• 7733 - ECP5 / Diamond 3.14: Why does my design get a Map device oversize error related to PLL for LFE5U-12F in with Diamond 3.14, but completes map successfully in earlier releases of Diamond software?

  In Diamond version 3.14, there is a bug where it incorrectly limits the number of PLLs in the device to 0 for LFE5U-12F. Example error message: ERROR - (device oversize error). The number of PLL components needed (1) exceeds the number available. ...

• 427 - Lattice Diamond: Why does synthesis tool prune counter bits away while they appear to be used in the equations?

  Depending on the coding style, signals in the Hardware Description Language (HDL) source code could be removed during the synthesis process. Most of the time it's very obvious why the signals are removed / pruned. But at times it's not clear to the ...

• 3514 - Diamond: Why is there a difference in the bitstream file size with a small logic modification in LatticeECP3?

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• 431 - ispVM System: How is bitstream programming verification (Verify) performed within Lattice ispVM System?

  The PLD programming verification with ispVM System performs a bit-for-bit compare of the device bitstream against the desired .JED file (as opposed to a less informational computed checksum comparison). This is easily verified by viewing the log file ...